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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 45/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
45 of 128
April, 2002
3.11 PHY Interface
3.11.1 General
The PHY Interface provides the connection between the L84302 and an
external Physical Layer device. There are two PHY Interfaces on the
L84302: (1) MII, and (2) 10 Mbps Serial. The MII (short for Media
Independent Interface) will operate in both 100 and 10 Mbps modes and
meets all the requirements outlined in IEEE 802.3 Clause 22. The 10
Mbps Serial Interface only operates at 10 Mbps and is compatible with
common industry standards for the 7-wire serial interface. The selection
of either MII or 10Mbps serial interface is done by appropriately setting
the PHY interface select bit in the TX command register. The device can
directly connect, without any external logic, to any Physical Layer device
which complies with the either IEEE 802.3 Clause 22 or the common 7-
wire 10 Mbps interface.
3.11.2 Data Format and Bit Order
The format and bit order of the MII and 10 Mbps serial data word on
TXD[3:0] and RXD[3:0] and its relationship to the MAC frame and the
System Interface data words is shown in
Figure 4
(for MII, this is same
format as specified in IEEE 802.3 Clause 22). Note that
Figure 4
has the
device in the little endian format (default). If the device is in the big
endian format, the byte order of the System Interface data word is
flipped. See
Section 3.3, “System Interface,” page 19
, for more details, if
needed.
3.11.3 MII Signals
The MII consists of fifteen signals per port: one transmit clock input
(TXC), four transmit data outputs (TXD[3:0]), one transmit enable output
(TXEN), one receive clock input (RXC), four receive data inputs
(RXD[3:0]), one carrier sense input (CRS), one receive data valid input
(RXDV), one receive data error input (RXER), and one collision input
CRC
OVFL
CRC Error
RX FIFO Over-
flow Error
1 = Receive packet has a CRC error
1 = Receive FIFO is full and more data is
attempting to be inputted
RXTXDATA1
RXTXDATA0
Symbol
Name
Definition
Position On
RXTXDATA[31:0] Pins
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