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| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 99/164頁(yè) |
| 文件大小： | 1148K |
| 代理商： | CTMRM |
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CTM
REFERENCE
MOTOROLA
9-5
PULSE WIDTH MODULATION SUBMODULE
For More Information On This Product,
Go to: www.freescale.com
9
comparisons can occur, but will have no effect on the output signal as the output flip-flop has
already been cleared.
The PWM output pulse may be as short as one PWM clock period (PWMB2 = $0001). It may be
as long as one PWM clock period less than the PWM period; for example, the pulse width equal
to 65535 PWM clock periods can be obtained by setting PWMB2 = $FFFF and PWMA2 = $0000.
9.2.5.1
0% and 100% ‘pulses’
The 0% and 100% ‘pulses’ are special limiting cases (zero width and infinite width) that are defined
by the ‘a(chǎn)lways clear’ and ‘a(chǎn)lways set’ states of the output flip-flop.
The 0% pulse is generated by making the pulse width value in PWMB2 equal to $0000. The output
is a true steady state signal with no glitches.
The 100% pulse is created by making the pulse width value in PWMB2 equal to or greater than
the period value in PWMA2. The output is a true steady state signal with no glitches.
Note:
It is not possible to have a 100% duty cycle when the output period is selected to be
65536 PWM clock periods (by setting PWMB2 = $0000); in this case the maximum duty
cycle is 99.998% (100 x 65535/65536).
When using the PWM output signal to generate analog levels, the 0% and 100% pulses provide
the full scale values.
Note:
Even when 0% or 100% pulses are being generated, the 16-bit PWM counter continues
to count and output changes to or from these limit values are done synchronously with
the selected period.
9.2.6
PWMSM coherency
Byte access of registers is discussed in Section 1.3.1, however, it should be noted that byte writes
to the double buffered registers PWMA1 and PWMB1 are not recommended as the transfer from
the primary registers to the secondary registers is done on a word basis.
For most PWMSM operations, 16-bit accesses are sufficient and long word accesses are treated
as two word accesses, with one exception — a long word write to the period/pulse width registers.
In this case, if the long word write is done within the PWM period, there is no visible effect on the
output signal and the new values are stored in PWMA1 and PWMB1 ready to be loaded into the
buffer registers at the start of the next period. If, however, the long word write coincides with the
end of the period, then the transfer of values from the primary registers to the secondary registers
is suppressed until the end of the next PWM period; during this period, the current values in the
secondary registers are used for the period and the pulse width.
F
.
Freescale Semiconductor, Inc.
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