參數(shù)資料
型號： CTMRM
英文描述： Configurable Timer Module Reference Manual
中文描述： 配置定時器模塊參考手冊
文件頁數(shù)： 63/164頁
文件大?。?/td> 1148K
代理商： CTMRM
CTM
REFERENCE
MOTOROLA
7-5
SINGLE ACTION SUBMODULE (SASM)
For More Information On This Product,
Go to: www.freescale.com
7
7.2.4
Output compare and toggle (OCT) mode
In OCT mode, the state of an output pin is toggled each time a successful output compare occurs;
an interrupt may also be generated. The output compare circuitry performs a comparison between
the 16-bit register and the selected time base bus. When a match is found, the output flip-flop is
toggled to the opposite state. At the same time, the FLAG bit is set to indicate to the processor that
the output compare has occurred. Depending on the state of the IEN bit, an interrupt can be
generated when the FLAG bit is set. The FLAG bit must be reset by software (see Section 7.2.1).
If the interrupt is serviced, the FLAG bit should be cleared by the servicing routine before returning
from that routine. If a subsequent output compare occurs while the FLAG bit is set, the output
toggles, and the FLAG bit remains set.
An output compare match can be simulated in software by writing a one to the FORCE bit. Setting
the FORCE bit forces the output flip flop to toggle as if an output compare had occurred. In this
case, the FLAG bit is not affected. Only if a genuine output compare occurs while doing a force,
will the FLAG bit be set to signify that the compare has occurred.
Note:
In OCT mode, the IN bit reflects the logic state on the output of the output flip-flop.
7.2.5
Output port (OP) mode
In OP mode the channel’s input/output pin is used as a single output port pin. The output compare
function is still available, but for internal operation only, and does not affect the state of the output
pin. An interrupt may also be generated when a compare occurs. The state of the output pin always
reflects the value of the EDOUT bit in the channel’s SIC register. Reading the EDOUT bit returns
the last value written to it.
The internal compare feature compares the 16-bit register with the selected time base bus. The
output compare circuitry performs a comparison between the 16-bit register and the selected time
base bus. When a match is found, the FLAG bit is set to indicate to the processor that the output
compare has occurred. Depending on the state of the IEN bit, an interrupt can be generated when
the FLAG bit is set. The FLAG bit must be reset by software (see Section 7.2.1). If the interrupt is
serviced, the FLAG bit should be cleared by the servicing routine before returning from that
routine. If a subsequent output compare occurs while the FLAG bit is set, the internal output
compare functions normally, and the FLAG bit remains set.
Note:
In OP mode, the IN bit value reflects the logic state on the output of the output flip-flop.
F
.
Freescale Semiconductor, Inc.
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