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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 67/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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CTM
REFERENCE
MOTOROLA
7-9
SINGLE ACTION SUBMODULE (SASM)
For More Information On This Product,
Go to: www.freescale.com
7
BSL — Time base bus select bit
This control bit selects the time base bus to be connected to SASM channel A. This bit is cleared
by reset.
1 (set)
–
Time base bus B selected.
0 (clear) –
Time base bus A selected.
IN — Input pin status bit
In input mode (IC), the IN bit reflects the logic state present on the corresponding input pin (after
being Schmitt triggered and synchronized).
In the output modes (OC, OCT and OP), the IN bit value reflects the state of the output of the output
flip-flop.
The IN bit is a read-only bit; writing to it has no effect. Reset has no effect on this bit.
FORCE — Force compare control bit
In the IC and OP modes, the FORCE bit is not used and writing to it has no effect.
In the OC and OCT modes, the FORCE bit is used by the software to cause the output flip-flop
(and the output pin) to behave as though an output compare had occurred. In OC mode, setting
the FORCE bit causes the value of EDOUT to be transferred to the output of the output flip-flop;
in OCT mode, setting the FORCE bit causes the output flip-flop to toggle. Internal synchronization
ensures that the correct level appears on the output pin when a new value is written to EDOUT
and FORCE is set at the same time.
1 (set)
–
Force output flip-flop to behave as if an output compare has just
occurred.
0 (clear) –
No action.
The FORCE bit is cleared by reset and always reads as zero.
Note:
The FLAG bit is not affected by the use of the FORCE bit.
EDOUT — Edge detect and output level bit
In IC mode, the EDOUT bit is used to select the edge that will trigger the input capture circuitry.
1 (set)
–
Input capture on rising edge.
0 (clear) –
Input capture on falling edge.
In OC mode, the EDOUT bit is used to latch the value to be output to the pin on the next output
compare match or when the FORCE bit is set. Internal synchronization ensures that the correct
level appears on the output pin when a new value is written to EDOUT and FORCE is set at the
same time. Reading EDOUT returns the previous value written.
F
.
Freescale Semiconductor, Inc.
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