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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 37/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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CTM
REFERENCE
MOTOROLA
3-1
INTERRUPTS
3
3
INTERRUPTS
This section describes the interrupt functions of the CTM and its submodules and how these
interrupts are passed to the CPU via the IMB. Interrupt requests from the CTM are treated as
exceptions by the CPU and are dealt with by the CPU’s exception processing routines. For a more
detailed description of exception processing in IMB based microprocessors, please refer to the
following Motorola publications:
–
–
CPU16 Central Processor Unit Reference Manual (CPU16RM/D)
CPU32 Central Processor Unit Reference Manual (CPU32RM/AD)
3.1
Interrupt levels on the IMB
The CTM and its submodules are capable of generating interrupts on eight different levels on the
intermodule bus (IMB). Interrupt levels, arbitration and a hardwired daisy-chain priority system of
the submodules in the CTM allow each of the many interrupt sources on the IMB to be uniquely
identified and to have a unique vector address.
Each CTM submodule contains an interrupt control register that sets the interrupt priority for the
submodule to one of eight levels (IL[2:0]). Level 7 is the highest priority level and level 0 disables
interrupts. (Note that the CPSM and the BIUSM do not have the capability to generate interrupts
and do not have interrupt vectors associated with them.)
When an interrupt is requested and is at a higher level than the current interrupt level set by the
interrupt or exception level mask in the CPU’s status register, the CPU starts an interrupt
acknowledge (IACK) cycle. The CTM compares the interrupt level it requested with the interrupt
level acknowledged by the CPU during the IACK cycle. If the levels match, arbitration with other
modules requesting service on the same interrupt level begins.
An interrupt of the same level as the CPU’s current interrupt or exception level mask cannot be
executed until the mask level reduces below that level, except for level 7 interrupts. Level 7 is non
maskable and exception processing on this level will be interrupted by other level 7 interrupts.
A higher level exception will interrupt a lower level exception routine, which must then wait until the
exception mask returns to its original level before continuing.
F
.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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