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| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 78/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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MOTOROLA
8-8
CTM
REFERENCE
DOUBLE ACTION SUBMODULE (DASM)
For More Information On This Product,
Go to: www.freescale.com
8
be used to perform a single output compare function, similar to the M68HC11 timer, or may be
used as an output port bit.
In this mode, channel B is accessed via register B2. Register B1 is not used and is not accessible
to the user. Both channels work together to generate one ‘single shot’ output pulse signal. Channel
A defines the leading edge of the output pulse, while channel B defines the trailing edge of the
pulse. FLAG setting can be done when a compare occurs on channel B only or when a compare
occurs on either channel (as defined by the MODE0 bit in the DASMSIC register).
When this mode is first selected, both comparators are disabled. Each comparator is enabled by
writing to its data register; it remains enabled until the next successful comparison is made on that
channel, whereupon it is disabled. The values stored in registers A and B are compared with the
count value on the selected time base bus when their corresponding comparators are enabled.
The output flip-flop is set when a match occurs on channel A. The output flip-flop is reset when a
match occurs on channel B. The polarity of the output signal is selected by the EDPOL bit. The
output flip-flop level can be obtained at any time by reading the IN bit.
If subsequent enabled output compares occur on channels A and B, the output pulses continue to
be output, regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop to the level
corresponding to a comparison on channel A or B, respectively. Note that the FLAG bit is not
affected by these ‘force’ operations.
Totem pole or open-drain output circuit configurations can be selected using the WOR bit in the
DASMSIC register.
Warning:
There is no hardware protection to disable comparator B while comparator A is enabled.
It is the user’s responsibility to load data registers A and B with the values needed to
produce the desired output pulse.
Note:
If both channels are loaded with the same value they will try to force different levels on
the output flip-flop. Hardware protection circuitry ensures that no contention occurs and
the output flip-flop provides a logic zero level output.
8.3.5.1
Single shot output pulse operation
The single shot output pulse operation is selected by writing the leading edge value of the desired
pulse to data register A and the trailing edge value to data register B. A single pulse will be output
at the desired time, thereby disabling the comparators until new values are written to the data
registers.
Note:
In this mode, registers A and B2 are accessible to the user software (at consecutive
addresses).
F
.
Freescale Semiconductor, Inc.
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