
CTM
REFERENCE
MOTOROLA
5-3
FREE-RUNNING COUNTER SUBMODULE (FCSM)
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5
desired number of events. When using the external clock source, the maximum guaranteed
external frequency is f
SYS
/4.
5.4
The FCSM time base bus driver
The DRVA and DRVB bits in the FCSMSIC register select the time base buses to be driven (see
Section 5.7.1). Which of the time base buses is driven depends on where the FCSM is physically
placed in any particular CTM implementation. See Section 1.4 for more information on the
structure of the time base buses. For examples of FCSM waveforms and timings, please refer to
Section 10.1.
Warning:
It is not recommended that the two time base buses be driven at the same time.
5.5
FCSM interrupts
A valid FCSM interrupt can be generated when the COF bit in the FCSMSIC register is set (as a
result of the counter overflowing). If the interrupt priority level of the FCSM is non-zero, as defined
by the three IL bits in the FCSMSIC register, a valid interrupt request will occur on the IMB.
5.6
Freeze action on the FCSM
When the IMB FREEZE signal is recognized, the FCSM counter stops counting and remains set
at its current value. When the FREEZE signal is negated, the counter starts incrementing from its
current value, as if nothing had happened. All registers are accessible during freeze.
During freeze, the IN bit in the FCSMSIC register continues to reflect the state of the signal on the
input pin CTMC (see Section 5.7.1).
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