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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 106/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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MOTOROLA
9-12
CTM
REFERENCE
PULSE WIDTH MODULATION SUBMODULE
For More Information On This Product,
Go to: www.freescale.com
9
EN — PWMSM enable control bit
The EN bit is a control bit that allows the software to enable and disable the PWMSM as required.
1 (set)
–
Enable the PWMSM and start generation of PWM output pulses.
0 (clear) –
Disable the PWMSM and stop generation of PWM output pulses.
While the PWMSM is disabled (EN = 0):
–
the output flip-flop is held reset and the level on the output pin is set to one
or zero according to the state of the POL bit,
the PWMSM’s divide-by-256 prescaler is held in reset,
the counter stops incrementing and is held equal to $0001,
the comparators are disabled,
and the PWMA1 and PWMB1 registers permanently transfer their contents
to the buffer registers (PWMA2 and PWMB2, respectively).
–
–
–
–
When the EN bit is changed from zero to one:
–
–
–
–
the output flip-flop is set to start the first pulse,
the PWMSM’s divide-by-256 prescaler is released,
the counter is released and starts to increment from $0001,
and the FLAG bit is set (to indicate that PWMA1 and PWMB1 can be
updated with new values of period and pulse width.
While EN is set, the PWMSM generates continuously a pulse width modulated output signal based
on the data in PWMA2 and PWMB2 (which are updated via PWMA1 and PWMB2 each time a
period is completed).
Note:
To prevent unwanted glitches on the output waveform when disabling the PWMSM, the
EN bit should not be cleared by the software until one period has been output as a 0%
pulse (PWMB2 = $0000).
CLK[2:0] — Clock rate selection bits
The CLK bits are control bits that allow the software to select one of the eight counter clock sources
coming from the PWMSM prescaler. These bits can be changed by the software at any time. Table
9-5 shows the counter clock sources and rates in detail.
9.4.2
PWMA — PWM period register
The PWMA register contains the period value for the next cycle of the PWM output waveform. In
normal usage, with the PWMSM enabled, the software writes a period value into PWMA1 and this
value is then loaded into the PWMA2 register at the end of the current period. If the PWMSM is
F
.
Freescale Semiconductor, Inc.
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