
MOTOROLA
7-2
CTM
REFERENCE
SINGLE ACTION SUBMODULE (SASM)
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7
A more detailed block diagram of a SASM channel is shown in Figure 7-2. Each channel
comprises:
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a time base bus selector (which selects the time base bus to be used by that
channel for all timing functions),
a 16-bit data register (which can be read by the software at any time and
which is used for both input capture and output compare functions),
a 16-bit comparator (which continuously compares the 16-bit value in the
data register with the time base bus),
an output flip-flop (which holds the logic level to be sent to the output pin
when a successful output compare occurs),
an input edge detector (which detects the rising or falling edge that will
trigger the input capture function),
several status and control bits in the status/interrupt/control register SICA or
SICB,
an interrupt section.
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–
–
–
–
–
Note:
During reset the output of the output flip-flop is cleared (i.e. to ‘zero’).
7.2
SASM modes of operation
Each SASM channel can operate in four different modes:
1. Input capture (IC) (i.e. either as input capture on a rising or falling edge or as
a read-only input port)
2. Output compare (OC)
3. Output compare and toggle (OCT)
4. Output port (OP)
Note:
For a channel operating in IC mode, the IN bit in the SIC register reflects the logic state
of the corresponding input pin (after being Schmitt triggered and synchronized). When
a channel is operating in OC, OCT or OP mode, the IN bit in the SIC register reflects
the logic state of the output of the output flip-flop.
7.2.1
Clearing and using the FLAG bits
To clear a FLAG bit, the software must first read the channel’s SIC register, then write a zero to the
FLAG bit. These two steps do not have to be done on consecutive instructions. This clearing
sequence must be used in every mode of operation. Writing a one to the FLAG bit has no effect.
F
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Freescale Semiconductor, Inc.