
MOTOROLA
4-2
CTM
REFERENCE
COUNTER PRESCALER SUBMODULE (CPSM)
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4
4.2
Freeze action on the CPSM
When the IMB FREEZE signal is recognized, the CPSM counters stop counting and remain set at
their current values. When the FREEZE signal is negated, the counters start incrementing from
their current values, as if nothing had happened. All registers are accessible during freeze.
4.3
CPSM registers
The CPSM register map comprises four 16-bit register locations. As shown in Table 4-1, the
register block contains two CPSM registers and two reserved registers. The CPSM register block
always immediately follows the BIUSM register block in the CPSM register map. All unused bits
and reserved address locations return zero when read by the software. Writing to unused bits and
reserved address locations has no effect.
Note:
All CPSM register addresses in this section are specified as offsets from the base
address of the CTM.
4.3.1
CPCR — CPSM control register
PRUN — Prescaler running bit
The PRUN bit is a read/write control bit that allows the software to switch the prescaler counter on
and off.
(1) Offset fromthe base address of the CTM.
(1) Offset fromthe base address of the CTM.
Table 4-1
CPSM register map
Address
(1)
$08
$0A
$0C
$0E
15
8 7
0
CPSMcontrol register (CPCR)
CPSMtest register (CPTR)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CPCR
$08
(1)
PRUN DIV23 PSEL1PSEL0
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
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Freescale Semiconductor, Inc.