參數(shù)資料
型號： CTMRM
英文描述： Configurable Timer Module Reference Manual
中文描述： 配置定時器模塊參考手冊
文件頁數(shù)： 74/164頁
文件大?。?/td> 1148K
代理商： CTMRM
MOTOROLA
8-4
CTM
REFERENCE
DOUBLE ACTION SUBMODULE (DASM)
For More Information On This Product,
Go to: www.freescale.com
8
8.3.1
Disable (DIS) mode
DIS mode is selected by making MODE[3:0] = 0000.
In this mode, all input capture and output compare functions of the DASM are disabled and the
FLAG bit is maintained in its reset state, but the input port pin function remains available. The
associated pin becomes a high impedance input and the input level on this pin is reflected by the
state of the IN bit in the DASMSIC register. All control and interrupt bits remain accessible, allowing
the software to prepare for future mode selection. Data registers A and B are accessible at
consecutive addresses. Writing to data register B stores the same value in registers B1 and B2.
Warning:
When changing modes, it is imperative to go through the DIS mode in order to reset the
DASM’s internal functions properly. Failure to do this could lead to invalid and
unexpected output compare or input capture results, and to flags being set incorrectly.
8.3.2
Input pulse width measurement (IPWM) mode
IPWM mode is selected by making MODE[3:0] = 0001.
This mode allows the width of a positive or negative pulse to be determined by capturing the
leading edge of the pulse on channel B and the trailing edge of the pulse on channel A; successive
captures are done on consecutive edges of opposite polarity. The edge sensitivity is selected by
the EDPOL bit in the DASMSIC register.
This mode also allows the software to determine the logic level on the input pin at any time by
reading the IN bit in the DASMSIC register.
The channel A input capture function remains disabled until the first rising edge triggers the first
input capture on channel B. When this rising edge is detected, the count value of the time base
bus selected by the BSL bit is latched in the 16-bit data register B1; the FLAG bit is not affected.
When the next falling edge is detected, the count value of the time base bus is latched into the
16-bit data register A and, at the same time, the FLAG bit is set and the contents of register B1 are
transferred to register B2. Reading data register B returns the value in register B2. If subsequent
input capture events occur while the FLAG bit is set, data registers A and B will be updated with
the latest captured values and the FLAG bit will remain set.
If a 32-bit coherent operation is in progress when the falling edge is detected, the transfer from B1
to B2 is deferred until the coherent operation is completed. Operation of the DASM then continues
on channels B and A as previously described.
The input pulse width is calculated by subtracting the value in data register B from the value in data
register A.
Figure 8-2 provides an example of how the DASM can be used for input pulse width measurement.
F
.
Freescale Semiconductor, Inc.
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