參數(shù)資料
型號： CTMRM
英文描述： Configurable Timer Module Reference Manual
中文描述： 配置定時器模塊參考手冊
文件頁數(shù)： 25/164頁
文件大?。?/td> 1148K
代理商： CTMRM
CTM
REFERENCE
MOTOROLA
1-5
FUNCTIONAL OVERVIEW
For More Information On This Product,
Go to: www.freescale.com
1
1.3.4
32-bit (long word) aligned accesses
A long word aligned access consists of two 16-bit aligned accesses (see Figure 1-4). When a long
word access is attempted, a signal line is activated on the SMB during the access of the high order
byte. This allows the CTM architecture to be compatible with submodules supporting long word
coherency.
1.3.5
32-bit (long word) misaligned accesses
A long word misaligned access consists of three accesses: first a byte access to an odd address
(see Figure 1-3), followed by a 16-bit aligned access to the following even address (see
Figure 1-4), followed by a byte access to the remaining even address (see Figure 1-2). Note that
the latter two accesses (16-bit aligned access followed by byte access to an even address)
represent what is called a 3-byte access. As there is no pipelining, coherency is not supported.
Note:
Neither CPU16 nor CPU32 support 32-bit misaligned accesses.
1.3.6
3-byte accesses
A 3-byte access is normally part of a long word misaligned access. It consists of a 16-bit aligned
access (see Figure 1-4), followed by a byte access to the remaining even address (see
Figure 1-2). A 3-byte access is treated by the BIUSM as a 16-bit aligned access. It is then the
responsibility of the bus master to access the following byte. As there is no pipelining, coherency
is not supported.
1.4
The time base bus system
The time base bus system is composed of four 16-bit buses: TBB1, TBB2, TBB3 and TBB4 (see
Figure 1-1). Typically, TBB2 and TBB3 are tied together to form a global bus (TBBB) while TBB1
and TBB4 remain as partial buses (collectively called TBBA).
How the submodules are connected to these time base buses is different for each CTM
configuration. This is shown generically in Figure 1-1, where all counter and action submodules in
the right half of the diagram (numbered from 1 to M-1) can be connected to TBB3 and/or TBB4,
and all submodules in the left half of the diagram (numbered from M to N) can be connected to
TBB1 and/or TBB2. An example of how the time base buses are configured and how the
submodules are connected to them in a practical CTM module (CTM2) is provided in Appendix B.
The time base buses are precharge/discharge type buses with wired-OR capability, so that no
hardware damage occurs when several counters are driving the same bus at the same time.
F
.
Freescale Semiconductor, Inc.
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