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參數(shù)資料
| 型號： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時器模塊參考手冊 |
| 文件頁數(shù)： | 75/164頁 |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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CTM
REFERENCE
MOTOROLA
8-5
DOUBLE ACTION SUBMODULE (DASM)
For More Information On This Product,
Go to: www.freescale.com
8
8.3.3
Input period measurement (IPM) mode
IPM mode is selected by making MODE[3:0] = 0010.
This mode allows the period of an input signal to be determined by capturing two consecutive
rising edges or two consecutive falling edges; successive input captures are done on consecutive
edges of the same polarity. The edge polarity is defined by the EDPOL bit in the DASMSIC register.
This mode also allows the software to determine the logic level on the input pin at any time by
reading the IN bit in the DASMSIC register.
When the first edge having the selected polarity is detected, the time base bus value is latched into
the 16-bit data register A, the data in register B1 is transferred to data register B2 and finally the
data in register A is transferred to register B1. On this first capture the FLAG bit is not set. On the
second and subsequent captures, the FLAG bit is set immediately before the data in register A is
transferred to register B1.
When the second edge of the same polarity is detected, the time base bus value is latched into
data register A, the data in register B1 is transferred to data register B2, the FLAG bit is set to
signify that the beginning and end points of a complete period have been captured, and finally data
register A is transferred to register B1. This sequence of events is repeated for each subsequent
capture. Reading data register B returns the value in register B2.
If a 32-bit coherent operation is in progress when an edge is detected, the transfer of data from B1
to B2 is deferred until the coherent operation is completed. At any time, the input level present on
the input pin can be read on the IN bit.
Figure 8-2
Input pulse width measurement example
Time base bus
$0500
$1000
$1100
$1250
$1525
$16A0
FLAG bit
DASMA captured value
1
B1 captured value
2
B2 value
1
$xxxx
$1000
$1000
$1250
$1250
$16A0
$xxxx
$xxxx
$1100
$1100
$1525
$1525
$xxxx
$xxxx
$1000
$1000
$1250
$1250
Input signal
Mode selection; EDPOL = 1
FLAG reset
by software
FLAG reset
by software
B
A
B
A
B
1. These values are accessible to the software.
2. These values are internal and are not accessible.
Notes:
F
.
Freescale Semiconductor, Inc.
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