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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 98/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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MOTOROLA
9-4
CTM
REFERENCE
PULSE WIDTH MODULATION SUBMODULE
For More Information On This Product,
Go to: www.freescale.com
9
9.2.4
PWMSM period registers and comparator
The period section of the PWMSM consists of two 16-bit period registers (PWMA1 and PWMA2)
and one 16-bit comparator. PWMA2 holds the current PWM period value and PWMA1 holds the
next PWM period value. The software establishes the next period of the output PWM signal by
writing a value into PWMA1. PWMA2 acts as a double buffer of PWMA1, allowing the contents of
PWMA1 to be changed at any time without affecting the current period of the output signal; it
cannot be accessed directly by the software. PWMA1 can be read or written at any time. The new
value in the PWMA1 register is transferred to PWMA2 on the next full cycle of the output or when
a ‘1’ is written to the LOAD bit in the PWMSIC register.
The comparator continuously compares the contents of the PWMA2 register with the value in the
PWMSM counter. When a match occurs, the state sequencer sets the output flip-flop and resets
the counter to $0001.
Period values $0000 and $0001 are special cases. When PWMA2 contains $0000, an output
period of 65536 PWM clock periods is generated.
When PWMA2 contains $0001, a period match occurs on every PWM clock period: the counter
never increments beyond $0001 and the output level never changes.
Note:
A value of $0002 in the period register and a value of $0001 in the pulse register are
the conditions necessary to obtain the maximum possible output frequency for a given
PWM clock period.
9.2.5
PWMSM pulse width registers and comparator
The pulse width section of the PWMSM consists of two 16-bit pulse width registers (PWMB1 and
PWMB2) and one 16-bit comparator. PWMB2 holds the current PWM pulse width value and
PWMB1 holds the next PWM pulse width value. The software establishes the next pulse width of
the output PWM signal by writing a value into PWMB1. Software may write a new pulse width value
into PWMB1 at any time and this new value will take effect at the start of the next PWM period (or
when the LOAD bit in the PWMSIC register is written to a ‘1’). The PWMSM hardware does not
modify the contents of PWMB1 at any time.
PWMB2 acts as a double buffer of PWMB1, allowing the contents of PWMB1 to be changed at any
time without affecting the current pulse width of the output signal; it cannot be accessed directly
by the software. PWMB1 can be read or written at any time. The new value in the PWMB1 register
is transferred to PWMB2 on the next full cycle of the output or when a ‘1’ is written to the LOAD bit
in the PWM SIC register
The pulse width comparator is a 16-bit ‘ones-equality’ comparator that compares the contents of
the PWMB2 register with the 16-bit PWM counter. When the counter reaches the value in PWMB2,
a match occurs and the output flip-flop is cleared. This pulse width match completes the pulse
width; it does not affect the counter. Since a ‘ones-equality’ comparator is used, subsequent
F
.
Freescale Semiconductor, Inc.
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