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參數(shù)資料
| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 49/164頁(yè) |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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CTM
REFERENCE
MOTOROLA
5-5
FREE-RUNNING COUNTER SUBMODULE (FCSM)
For More Information On This Product,
Go to: www.freescale.com
5
IL[2:0] — Interrupt level bits
The three interrupt level bits are read/write control bits that select the priority level of interrupt
requests made by the FCSM. These bits can be read or written at any time and are cleared by reset.
IARB3 — Interrupt arbitration bit 3
The read/write IARB3 bit works in conjunction with the IARB[2:0] field in the BIUSM module
configuration register. Each module that generates interrupt requests on the IMB must have a
unique value in the arbitration field (IARB). This interrupt arbitration identification number is used
to arbitrate for the IMB when modules generate simultaneous interrupts of the same priority (see
Section 3). The IARB3 bit is cleared by reset.
DRVA, DRVB — Drive time base bus bits
DRVA and DRVB are read/write bits that control the connection of the FCSM to the time base buses
A and B. These bits are cleared by reset. (See Section 1.4 for information on the time base buses.)
Warning:
It is not recommended that the two time base buses be driven at the same time.
IN — Input pin status bit
This read-only status bit reflects the logic state of the FCSM input pin CTMC. Writing a ‘zero’ or a
‘one’ to this bit has no effect. Reset has no effect on this bit.
IL2
0
0
0
0
1
1
1
1
IL1
0
0
1
1
0
0
1
1
IL0
0
1
0
1
0
1
0
1
Selected level
Interrupt disabled
Interrupt level 1 (lowest)
Interrupt level 2
Interrupt level 3
Interrupt level 4
Interrupt level 5
Interrupt level 6
Interrupt level 7 (highest)
DRVA
0
0
1
1
DRVB
0
1
0
1
Bus selected
Neither time base bus A nor time base bus B is driven
Time base bus B is driven
Time base bus A is driven
Both time base bus A and time base bus B are driven
F
.
Freescale Semiconductor, Inc.
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