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參數(shù)資料
| 型號： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時器模塊參考手冊 |
| 文件頁數(shù)： | 64/164頁 |
| 文件大?。?/td> | 1148K |
| 代理商： | CTMRM |
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MOTOROLA
7-6
CTM
REFERENCE
SINGLE ACTION SUBMODULE (SASM)
For More Information On This Product,
Go to: www.freescale.com
7
7.3
SASM interrupts
Each channel in the dual-channel SASM has separately enabled and initiated interrupts and they
each have their own unique vector number and address. However, they are both assigned to the
same interrupt level and arbitration priority by the IL[2:0] and IARB3 bits in the SICA register.
A valid SASM interrupt is recognized when the FLAG bit is set, the corresponding IEN bit is set
and the interrupt level defined by bits IL[2:0] is not equal to zero.
The FLAG bit is a status bit that indicates, when set, that an input capture or output compare has
occurred on the corresponding single action channel.
The relative priority of these sources of interrupt is fixed and channel A has a higher priority than
channel B.
7.4
Freeze action on the SASM
When the IMB FREEZE signal is recognized, the SASM input capture and output compare
functions are halted. As soon as the FREEZE signal is negated, SASM actions resume as if
nothing had happened. During freeze, the IN bits of the SIC registers (SICA and SICB) are
readable and return the levels present at the input pins if an input mode is in operation, or the
output value if an output mode is in operation (see Section 7.5.1 and Section 7.5.3). When one of
the output modes is in operation, the force output function remains available, allowing the software
to output the desired level (a useful feature for debugging). All SASM registers are accessible
during freeze.
7.5
SASM registers
The SASM register map comprises eight 16-bit register locations. As shown in Table 7-1, the
register block contains two SASM registers for each channel and four reserved registers. All
unused bits and reserved address locations return zero when read by the software. Writing to
unused bits and reserved address locations has no meaning nor effect. All register addresses in
this section are specified as offsets from the base address of the SASM. In CTM implementations
featuring multiple SASMs, each SASM has its own set of registers.
F
.
Freescale Semiconductor, Inc.
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