參數(shù)資料
型號(hào)： CTMRM
英文描述： Configurable Timer Module Reference Manual
中文描述： 配置定時(shí)器模塊參考手冊(cè)
文件頁數(shù)： 41/164頁
文件大?。?/td> 1148K
代理商： CTMRM
CTM
REFERENCE
MOTOROLA
4-1
COUNTER PRESCALER SUBMODULE (CPSM)
For More Information On This Product,
Go to: www.freescale.com
4
4
COUNTER PRESCALER SUBMODULE
(CPSM)
4.1
CPSM description
The counter prescaler submodule (CPSM) is a programmable divider system that provides the
CTM counters with a choice of six clock signals (PCLKx) derived from the main MCU system clock
(f
SYS
). The first counter prescaler stage generates PCLK1 by dividing f
SYS
by 2 or by 3. The output
of this first counter is then applied to an 8-bit prescaler which divides the clock signal further (by
2, 4, 8 and 16) to produce PCLK2, PCLK3, PCLK4 and PCLK5 (respectively). The division ratio
for PCLK6 is software selectable (using the PSEL[1:0] control bits in the counter prescaler control
register) from divide by 32, 64, 128 and 256. A block diagram of the CPSM is given in Figure 4-1.
The clock division ratios available on PCLKx are also shown in the table in Section 4.3.1. These
clock signals are provided on the SMB and may be used by any or all CTM submodules.
Figure 4-1
CPSM block diagram
f
SYS
8-bit
prescaler
PCLK2 =
PCLK3 =
PCLK4 =
PCLK5 =
PCLK6 =
First CPSM
prescaler
Select
PCLK1 =
/2
/4
/8
/16
/32
/64
/128
/256
PRUN DIV23 PSEL1 PSEL0
CPCR
/2 or /3
f
SYS
/2
f
SYS
/4
f
SYS
/8
f
SYS
/16
f
SYS
/32
f
SYS
/64
f
SYS
/128
f
SYS
/256
f
SYS
/512
f
SYS
/3
f
SYS
/6
f
SYS
/12
f
SYS
/24
f
SYS
/48
f
SYS
/96
f
SYS
/192
f
SYS
/384
f
SYS
/768
DIV23 = /3
DIV23 = /2
F
.
Freescale Semiconductor, Inc.
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