
MOTOROLA
8-10
CTM
REFERENCE
DOUBLE ACTION SUBMODULE (DASM)
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8
8.3.6
Output pulse width modulation (OPWM) mode
OPWM mode is selected by making MODE[3:0] = 1xxx. The MODE[2:0] bits allow some of the
comparator bits to be masked.
This mode allows pulse width modulated output waveforms to be generated, with eight selectable
frequencies (for a given time base). Both channels (A and B) are used to generate one PWM
output signal on the DASM pin.
Channel B is accessed via register B1. Register B2 is not accessible to the user. Channels A and
B define the leading and trailing edges, respectively, of the PWM output pulse. The value in register
B1 is continuously transferred to register B2 in the time between each trailing edge and the
following leading edge.
The value loaded in register A is continuously compared with the value on the time base bus. When
a match on A occurs, the FLAG bit is set and the output flip-flop is set. The value loaded in register
B2 is continually compared with the value on the time base bus. When a match occurs on B, the
output flip-flop is reset.
The polarity of the PWM output signal is selected by the EDPOL bit. The output flip-flop level can
be obtained at any time by reading the IN bit.
If subsequent compares occur on channels A and B, the PWM pulses continue to be output,
regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop to the level
corresponding to comparison on A or B respectively. Note that the FLAG bit is not affected by the
FORCA and FORCB operations.
Figure 8-6
Single shot output transition example
Time base bus
$0500
$1000
$1100
$1000
$1100
$1000
FLAG bit
DASMA value
1
B2 value
1
$xxxx
$xxxx
$1100
$1100
$xxxx
$1000
$1000
$1000
Input signal
Mode selection; MODE0 = 1
FLAG reset
by software
FLAG reset
by software
A
B
Write to B
Write to A
1. These values are accessible to the software.
Note:
F
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