
MOTOROLA
9-6
CTM
REFERENCE
PULSE WIDTH MODULATION SUBMODULE
For More Information On This Product,
Go to: www.freescale.com
9
9.2.7
PWMSM interrupts
The FLAG bit in the PWMSIC register is set when a new period begins and indicates that the
period and pulse width registers (PWMA1 and PWMB1) may be updated with values for the next
output period and pulse width. When the FLAG bit is set, an interrupt request is generated on one
of eight levels as defined by the interrupt level bits (IL[2:0]) in the PWMSIC register. If the interrupt
level is set to zero, interrupts are disabled.
9.2.8
Freeze action on the PWMSM
When the IMB FREEZE signal is recognized, the PWMSM counter stops incrementing and
remains set at its last value. When the FREEZE signal is negated, the counter starts incrementing
from its last value, as if nothing had happened.
9.3
PWM frequency, pulse width and resolution
Table 9-1 and Table 9-2 shows the pulse widths and frequencies that can be achieved using the /2
and /3 options and a clock frequency of 16.78 MHz.
Table 9-1
PWM pulse and frequency ranges (in Hz) using /2 option (16.78 MHz)
Mnimum
pulse width
Bits of resolution
9
16
15
14
13
12
11
10
8
7
6
5
4
3
2
1
0.119
μ
s
0.238
μ
s
0.477
μ
s
0.954
μ
s
1.91
μ
s
3.81
μ
s
7.63
μ
s
30.5
μ
s
/2
/4
/8
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
131k
262k
524k
1049k
2097k 4195kk
64
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
131k
262k
524k
1049k
2097k
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
131k
262k
524k
1049k
/16
/32
/64
/128
/512
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
131k
262k
524k
8.0
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
131k
262k
4.0
8.0
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
131k
2.0
4.0
8.0
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65.5k
0.5
1.0
2.0
4.0
8.0
16
32
64
128
256
512
1024
2048
4096
8192
16384
F
.
Freescale Semiconductor, Inc.