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| 型號(hào)： | CTMRM |
| 英文描述： | Configurable Timer Module Reference Manual |
| 中文描述： | 配置定時(shí)器模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 62/164頁(yè) |
| 文件大小： | 1148K |
| 代理商： | CTMRM |
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MOTOROLA
7-4
CTM
REFERENCE
SINGLE ACTION SUBMODULE (SASM)
For More Information On This Product,
Go to: www.freescale.com
7
7.2.2
Input capture (IC) mode
In IC mode, the 16-bit counter value on the selected time base bus is ‘captured’ when a triggering
event occurs on the channel’s input pin. Triggering of the input capture circuitry is done by a rising
or falling edge on the input pin; the polarity of the triggering edge is selected by the EDOUT bit.
The logic level on the input pin can be read by software via the IN bit in the channel’s SIC register.
Note:
In IC mode, the input pin is Schmitt triggered and the input signal is synchronized to the
system clock (f
SYS
). The IN bit reflects the state present on the input pin (after being
Schmitt triggered and synchronized).
When an input capture occurs, the count value on the selected time base bus is latched into the
channel’s 16-bit data register. At the same time, the FLAG bit in the SIC register is set to indicate
that an input capture has occurred.
The FLAG bit must be reset by software (see Section 7.2.1). If the interrupt is serviced, the FLAG
bit should be cleared by the servicing routine before returning from that routine. If a subsequent
input capture event occurs while the FLAG bit is set, the new captured counter value is latched,
and the FLAG bit remains unchanged.
Note:
In IC mode, the value of the EDOUT bit is permanently transferred to the output flip-flop.
This value will be output on the pin when the mode is changed to one of the output
modes.
7.2.3
Output compare (OC) mode
In OC mode, the state of an output pin is changed when a successful output compare occurs; an
interrupt may also be generated. The output compare circuitry performs a comparison between the
16-bit register and the selected time base bus. When a match is found, the EDOUT bit value is
transferred to the output flip-flop. At the same time, the FLAG bit is set to indicate to the processor
that a match has occurred. Depending on the state of the IEN bit, an interrupt can be generated
when the FLAG bit is set. The FLAG bit must be reset by software (see Section 7.2.1). If the
interrupt is serviced, the FLAG bit should be cleared by the servicing routine before returning from
that routine. If a subsequent output compare occurs while the FLAG bit is set, the output compare
function occurs normally, and the FLAG bit remains set.
An output compare match can be simulated in software by writing a one to the FORCE bit. Setting
the FORCE bit forces the EDOUT bit value onto the pin as if an output compare had occurred. In
this case, the FLAG bit is not affected. Only if a genuine output compare occurs while doing a force,
will the FLAG bit be set to signify that the compare has occurred.
Note:
In OC mode, the IN bit value reflects the logic state on the output of the output flip-flop.
F
.
Freescale Semiconductor, Inc.
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