
CTM
REFERENCE
MOTOROLA
8-11
DOUBLE ACTION SUBMODULE (DASM)
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8
Warning:
There is no hardware protection to disable comparator B while comparator A is enabled.
It is the user’s responsibility to load data registers A and B with the values needed to
produce the desired PWM output pulse.
Note:
If both channels are loaded with the same value they will try to force different levels on
the output flip-flop. Hardware protection circuitry ensures that no contention occurs and
the output flip-flop provides a logic zero level output.
Figure 8-7 provides an example of how the DASM can be used for pulse width modulation.
To generate PWM output pulses of different frequencies, the 16-bit comparator can have some of
its bits masked. This is controlled by bits MODE2, MODE1 and MODE0. The frequency of the
PWM output (f
PWM
) is given by the following equation (assuming the DASM is connected to a free
running counter):
[1]
where N
CPSM
is the overall CPSM clock divide ratio (
÷
2 to
÷
512 or
÷
3 to
÷
768) and N
DASM
is the
DASM divide ratio.
A few examples of frequencies and resolutions that can be obtained are shown in Table 8-2.
Figure 8-7
DASM output pulse width modulation example
Time base bus
$1000
$1100
$0000
$1000
$1500
$1700
FLAG bit
DASMA value
1
B1 value
1
B2 value
2
$xxxx
$1500
$1500
$1700
$1700
$1000
$1000
$1000
$1000
$1000
$xxxx
$xxxx
$1500
$1700
$1700
PWMoutput
EDPOL = 0
FLAG reset
by software
FLAG reset
by software
B2 comparison
matches
Write
A comparison
matches
B2 comparison
matches
B1 = $1700
Write
B1 = $1500
A comparison
matches
$1000
$1700
$1700
1. These values are accessible to the software.
2. These values are internal and are not accessible.
Notes:
f
PWM
f
CPSM
N
DASM
N
=
F
.
Freescale Semiconductor, Inc.