CPU16
REFERENCE MANUAL
MOTOROLA
vii
(Continued)
TABLE OF CONTENTS
9.7.2.1
9.7.2.2
9.7.2.3
9.7.2.4
9.8
Illegal Instructions ...................................................................9-14
Division By Zero ......................................................................9-15
BGND Instruction ....................................................................9-15
SWI Instruction ........................................................................9-15
Return from Interrupt (RTI) ......................................................................9-15
SECTION 10 DEVELOPMENT SUPPORT
10.1
10.1.1
10.1.2
10.1.3
10.1.3.1
10.1.3.2
10.1.3.3
10.1.3.4
10.1.3.5
10.1.3.6
10.1.4
10.1.5
10.2
10.3
10.4
10.4.1
10.4.2
10.4.2.1
10.4.2.2
10.4.2.3
10.4.2.4
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.7.1
10.4.7.2
10.4.8
10.4.9
10.4.10
10.4.10.1
10.4.11
10.4.12
Deterministic Opcode Tracking ...............................................................10-1
Instruction Pipeline ..........................................................................10-1
IPIPE0/IPIPE1 Multiplexing .............................................................10-2
Pipeline State Signals .....................................................................10-3
NULL — No Instruction Pipeline Activity .................................10-3
START — Instruction Start ......................................................10-3
ADVANCE — Instruction Pipeline Advance ............................10-4
FETCH — Instruction Fetch ....................................................10-4
EXCEPTION — Exception Processing in Progress ................10-4
INVALID — PHASE1/PHASE2 Signal Invalid .........................10-4
Combining Opcode Tracking with Other Capabilities ......................10-5
CPU16 Instruction Pipeline State Signal Flow ................................10-5
Breakpoints .............................................................................................10-5
Opcode Tracking and Breakpoints ..........................................................10-8
Background Debugging Mode (BDM) .....................................................10-8
Enabling BDM ...............................................................................10-10
BDM Sources ................................................................................10-11
BKPT Signal ..........................................................................10-11
BGND Instruction ..................................................................10-11
Microcontroller Module Breakpoints ......................................10-11
Double Bus Fault ...................................................................10-11
BDM Signals ..................................................................................10-11
Entering BDM ................................................................................10-12
Command Execution .....................................................................10-12
Returning from BDM ......................................................................10-13
BDM Serial Interface .....................................................................10-13
CPU Serial Logic ...................................................................10-15
Development System Serial Logic ........................................10-16
BDM Command Format ................................................................10-18
Command Sequence Diagram ......................................................10-18
BDM Command Set ......................................................................10-20
BDM Memory Commands and Bus Errors ............................10-20
Future Commands .........................................................................10-37
Recommended BDM Connection ..................................................10-37
F
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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