MOTOROLA
A-8
COMPARISON OF CPU16/M68HC11 CPU ASSEMBLY LANGUAGE
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CPU16
REFERENCE MANUAL
A.4.4 CLI
The CLI instruction has been replaced by ANDP. ANDP performs AND between the
content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[0:3]) is
not affected.
The following code can be used to clear the IP field in the CCR:
ANDP #$FF1F
The ANDP instruction can clear the entire CCR, except for the PK extension field, at
once.
A.4.5 CLV
The CLV instruction has been replaced by ANDP. ANDP performs AND between the
content of the condition code register and an unsigned immediate operand, then
replaces the content of the CCR with the result. The PK extension field (CCR[0:3]) is
not affected.
The following code can be used to clear the V bit in the CCR:
ANDP #$FDFF
The ANDP instruction can clear the entire CCR, except for the PK extension field, at
once.
A.4.6 DES
The DES instruction has been replaced by AIS. AIS adds a 20-bit value to concate-
nated SK and SP. The 20-bit value is formed by sign-extending an 8-bit or 16-bit
signed immediate operand.
The following code can be used to perform a DES:
AIS –1
CPU16 stacking operations normally use 16-bit words and even word addresses,
while M68HC11 CPU stacking operations normally use bytes and byte addresses. If
the CPU16 stack pointer is misaligned as a result of a byte operation, performance can
be degraded.
A.4.7 DEX
The DEX instruction has been replaced by AIX. AIX adds a 20-bit value to concate-
nated XK and IX. The 20-bit value is formed by sign-extending an 8-bit or 16-bit signed
immediate operand.
The following code can be used to perform a DEX:
AIX –1
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