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型號(hào)：	CPU16RM
英文描述：	M68HC16 Family CPU16 Reference Manual
中文描述：	M68HC16家庭CPU16參考手冊(cè)
文件頁(yè)數(shù)：	377/482頁(yè)
文件大?。?/td>	2417K
代理商：	CPU16RM

REFERENCE MANUAL

INSTRUCTION TIMING

8.2.2.3 Change-of-Flow Instructions

Operand access for change of flow instructions varies according to type. Unary

branches, conditional branches, and jumps have no operand access. Bit-condition

branches must make one memory access in order to perform masking. Subroutine

and interrupt instructions must make stack accesses.

In addition, when an instruction that can cause a change in flow executes, no prefetch

is made until after the precondition for change of flow is evaluated.

There are two evaluation cases:

If the instruction causes an unconditional change, or meets a specific precondition

for change, the program counter is loaded with the first address of a new instruction

stream, and the pipeline is filled with new instructions.

If the instruction does not meet a specific precondition (preconditions of unary

branches are always true or always false), prefetch is made and execution of the

old instruction stream resumes.

shows the number of program and operand access cycles for each instruc-

tion that causes a change in program flow.

In program access values for conditional branches, the first value is for branch taken, the second value is for branch

Table 8-2 Change-of-Flow Instruction Timing

Unary branch (1 = 1)

Unary branch (1 = 0)

Conditional branches

Unary branch (1 = 1)

Unary branch (1 = 0)

Conditional branches

Bit-condition branch,

IND8 addressing mode

Bit-condition branch,

EXT, IND16 addressing modes

Bit-condition branch,

IND8 addressing mode

Bit-condition branch,

EXT, IND16 addressing modes

Unconditional

Operand accesses include stack access

and vector fetch

Operand accesses include stack access

Short Branches

Long Branches

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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