MOTOROLA
6-102
INSTRUCTION GLOSSARY
CPU16
REFERENCE MANUAL
EDIVS
Operation:
Extended Signed Integer Divide
EDIVS
(E : D)
/
(IX)
IX
Remainder
D
Description:
Divides a 32-bit signed dividend contained in concatenated accumu-
lators E and D by a 16-bit divisor contained in index register X. The
quotient is placed in IX and the remainder in D. There is an implied
radix point to the right of IX0. Implied radix points in dividend and di-
visor must occupy the same bit position.
The states of condition code register bits N, Z, and C are undefined
after overflow. The states of bits N, Z, V, and C are undefined after
division by zero, but accumulator contents are not changed. Division
by zero causes an exception. See
SECTION 9 EXCEPTION PRO-
CESSING
for more information.
Syntax:
Standard
Condition Code Register:
S:
Not affected.
Not affected.
Not affected.
Not affected.
Set if IX15
=
1 as a result of operation; else cleared. Undefined after overflow or division by zero.
Set if (IX)
=
$0000 as a result of operation; else cleared. Undefined after overflow or division by zero.
Set if (IX)
>
$7FFF for a positive quotient or if (IX)
>
$8000 for a negative quotient as a result of operation;
else cleared. Undefined after division by zero.
C:
Set if
2
Remainder
≥
Divisor
; else cleared. Undefined after overflow or division by zero.
IP:
Not affected.
SM:
Not affected.
PK:
Not affected.
Instruction Format:
MV:
H:
EV:
N:
Z:
V:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
MV
H
EV
N
Z
V
C
IP
SM
PK
—
—
—
—
—
—
—
Addressing Mode
INH
Opcode
3729
Operand
—
Cycles
38
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.