CPU16
REFERENCE MANUAL
INSTRUCTION GLOSSARY
MOTOROLA
6-273
ASRM
Arithmetic Shift Right
AM
INH
27BA
—
4
—
—
—
—
—
ASRW
Arithmetic Shift Right
Word
IND16, X
IND16, Y
IND16, Z
EXT
REL8
270D
271D
272D
273D
B4
gggg
gggg
gggg
hh ll
rr
8
8
8
8
—
—
—
—
BCC
2
BCLR
Branch if Carry Clear
If C = 0, branch
6, 2
—
—
—
—
—
—
—
—
Clear Bit(s)
(M)
(Mask)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND16, X
1708
1718
1728
08
18
28
38
2708
mm ff
mm ff
mm ff
mm gggg
mm gggg
mm gggg
mm hh ll
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
rr
8
8
8
8
8
8
8
10
—
—
—
—
0
—
BCLRW
Clear Bit(s) in a Word
(M : M + 1)
(Mask)
M : M + 1
IND16, Y
IND16, Z
EXT
2718
2728
2738
10
10
10
—
—
—
—
0
—
BCS
2
BEQ
2
BGE
2
Branch if Carry Set
If C = 1, branch
REL8
B5
6, 2
—
—
—
—
—
—
—
—
Branch if Equal
If Z = 1, branch
REL8
B7
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Greater Than
or Equal to Zero
Enter Background
Debug Mode
If N
⊕
V = 0, branch
REL8
BC
rr
6, 2
—
—
—
—
—
—
—
—
BGND
If BDM enabled,
begin debug;
else, illegal instruction trap
If Z
(N
⊕
V) = 0, branch
INH
37A6
—
—
—
—
—
—
—
—
—
—
BGT
2
Branch if Greater Than
Zero
Branch if Higher
REL8
BE
rr
6, 2
—
—
—
—
—
—
—
—
BHI
2
BITA
If C
Z = 0, branch
REL8
B2
rr
6, 2
—
—
—
—
—
—
—
—
Bit Test A
(A)
(M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
REL8
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
C9
D9
E9
F9
17C9
17D9
17E9
17F9
27C9
27D9
27E9
BF
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
rr
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
0
—
BITB
Bit Test B
(B)
(M)
—
—
—
—
0
—
BLE
2
Branch if Less Than or
Equal to Zero
Branch if Lower or
Same
Branch if Less Than
Zero
Branch if Minus
If Z
(N
⊕
V) = 1, branch
6, 2
—
—
—
—
—
—
—
—
BLS
2
If C
Z = 1, branch
REL8
B3
rr
6, 2
—
—
—
—
—
—
—
—
BLT
2
If N
⊕
V = 1, branch
REL8
BD
rr
6, 2
—
—
—
—
—
—
—
—
BMI
2
BNE
2
BPL
2
If N = 1, branch
REL8
BB
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Not Equal
If Z = 0, branch
REL8
B6
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Plus
If N = 0, branch
REL8
BA
rr
6, 2
—
—
—
—
—
—
—
—
Table 6-36 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
Z
V
C
F
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.