CPU16
REFERENCE MANUAL
INSTRUCTION SET
MOTOROLA
5-17
LBSR and JSR are 4-byte instructions. For program execution to re-
sume at the instruction immediately following them, RTS must sub-
tract $0002 from the stacked PK
:
PC value.
BSR is a 2-byte instruction. BSR subtracts $0002 from the stacked
value prior to stacking so that RTS will work correctly.
5.6.6 Interrupt Instructions
The SWI instruction initiates synchronous exception processing. First, return PC and
CCR values are stacked (stacking the CCR saves the PK extension field). After return
values are stacked, the PK field is cleared, and the PC is loaded with exception vector
6 (content of address $000C).
The RTI instruction is used to terminate all exception handlers, including interrupt ser-
vice routines. It causes normal execution to resume with the instruction following the
last instruction that executed prior to interrupt. See
SECTION 9 EXCEPTION PRO-
CESSING
for more information.
Note
Instruction pipelining affects the operation of SWI. When an interrupt
occurs, PK
:
PC contain the address of the interrupted instruction
plus $0006. This value is stacked during asynchronous exception
processing, but synchronous exceptions, such as SWI, must adjust
the stacked value so that RTI can work correctly.
For program execution to resume with the interrupted instruction fol-
lowing an asynchronous interrupt, RTI must subtract $0006 from the
stacked PK
:
PC value.
Synchronous interrupts allow an interrupted instruction to finish exe-
cution before exception processing begins. The SWI instruction must
add $0002 prior to stacking in order for execution to resume correct-
ly.
Table 5-25 Interrupt Summary
Mnemonic
RTI
Function
Operation
Return from Interrupt
(SK : SP) + 2
SK : SP
Pull CCR
(SK : SP) + 2
SK : SP
Pull PC
(PK : PC) – 6
PK : PC
(PK : PC) + 2
PK : PC
Push (PC)
(SK : SP) – 2
SK : SP
Push (CCR)
(SK : SP) – 2
SK : SP
$0
PK
SWI Vector
PC
SWI
Software Interrupt
F
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n
.