CPU16
REFERENCE MANUAL
DEVELOPMENT SUPPORT
MOTOROLA
10-15
Bit 16 indicates status of CPU-generated messages as shown in
Table 10-4
.
Command and data transfers initiated by the development system must clear bit 16.
All commands that return a result return 16 bits of data plus one status bit.
10.4.7.1 CPU Serial Logic
CPU16 serial logic, shown in the left-hand portion of
Figure 10-9
, consists of transmit
and receive shift registers and of control logic that includes synchronization, serial
clock generation circuitry, and a received bit counter.
Both DSCLK and DSI are synchronized to internal clocks. Data is sampled during the
high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made
available to internal logic. If there is no synchronization between CPU16 and develop-
ment system hardware, the minimum hold time on DSI with respect to DSCLK is one
full period of CLKOUT.
Serial transfer is based on the DSCLK signal (see
Figure 10-11
). At the rising edge of
the internal synchronized DSCLK, synchronized data is transferred to the input shift
register, and the received bit counter is decremented. One-half clock period later, the
output shift register is updated, bringing the next output bit to the DSO signal. DSO
changes relative to the rising edge of DSCLK and does not necessarily remain stable
until the falling edge of DSCLK.
Table 10-4 CPU Generated Message Encoding
Bit 16
0
0
1
1
Data
xxxx
FFFF
0000
FFFF
Message Type
Valid Data Transfer
Command Complete; Status OK
Not Ready with Response; Come Again
Illegal Command
F
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n
.