
MOTOROLA
3-4
SYSTEM RESOURCES
CPU16
REFERENCE MANUAL
3.2.5 Condition Code Register
The 16-bit condition code register can be divided into two functional blocks. The eight
MSB, which correspond to the CCR in the M68HC11, contain the low-power stop con-
trol bit and processor status flags. The eight LSB contain the interrupt priority field, the
DSP saturation mode control bit, and the program counter address extension field.
Management of interrupt priority in the CPU16 differs considerably from that of the
M68HC11. See
SECTION 9 EXCEPTION PROCESSING
for complete information.
Figure 3-2
shows the condition code register. Detailed descriptions of each status in-
dicator and field in the register follow the figure.
Figure 3-2 Condition Code Register
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed
1 = Perform NOP when LPSTOP instruction is executed
MV — Accumulator M Overflow Flag
Set when overflow into AM35 has occurred.
H — Half Carry Flag
Set when a carry from bit 3 in A or B occurs during BCD addition.
EV — Extension Bit Overflow Flag
Set when an overflow into AM31 has occurred.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when two’s complement overflow occurs as the result of an operation.
C — Carry Flag
Set when carry or borrow occurs during arithmetic operation. Also used during shift
and rotate to facilitate multiple word operations.
IP[2:0] — Interrupt Priority Field
The priority value in this field (0 to 7) is used to mask interrupts.
SM — Saturate Mode Bit
When SM is set, if either EV or MV is set, data read from AM using TMER or TMET
will be given maximum positive or negative value, depending on the state of the AM
sign bit before overflow.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
MV
H
EV
N
Z
V
C
IP
SM
PK
F
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n
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