
Intel
Celeron Processor up to 700 MHz
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Datasheet
Tables
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Processor Identification.......................................................................................11
Voltage Identification Definition ..........................................................................18
Intel
Celeron Processor System Bus Signal Groups.....................................20
Absolute Maximum Ratings ...............................................................................22
Voltage and Current Specifications ....................................................................23
AGTL+ Signal Groups DC Specifications ...........................................................27
Non-AGTL+ Signal Group DC Specifications
.....................................................28
Processor AGTL+ Bus Specifications ................................................................29
System Bus AC Specifications (Clock) at the Processor
Edge Fingers (for S.E.P. Package)
....................................................................30
System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages) ................................................31
Valid Intel
Celeron Processor System Bus, Core Frequency
.......................32
System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Edge Fingers (for S.E.P. Package)....................................................32
System Bus AC Specifications (AGTL+ Signal Group) at
the Processor Core Pins (for S.E.P. Package) ..................................................33
Processor System Bus AC Specifications (AGTL+ Signal Group)
at the Processor Core Pins (for PPGA Package) ...............................................33
System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins (for FC-PGA Package)......................................................34
System Bus AC Specifications (CMOS Signal Group) at the
Processor Edge Fingers (for S.E.P. Package) ...................................................34
System Bus AC Specifications (CMOS Signal Group) at
the Processor Core Pins (for Both S.E.P. and PGA Packages) .........................35
System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages) ..............................................................35
System Bus AC Specifications (Reset Conditions)
(for the FC-PGA Package) .................................................................................36
System Bus AC Specifications (APIC Clock and APIC I/O)
at the Processor Edge Fingers (for S.E.P. Package) .........................................36
System Bus AC Specifications (APIC Clock and APIC I/O)
at the Processor Core Pins (For S.E.P. and PGA Packages)
............................37
System Bus AC Specifications (TAP Connection) at the
Processor Edge Fingers (For S.E.P. Package) ..................................................38
System Bus AC Specifications (TAP Connection) at the
Processor Core Pins (for Both S.E.P. and PPGA Packages) ............................39
BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages)...............................................................44
BCLK/PICCLK Signal Quality Specifications for Simulation
at the Processor Pins (for the FC-PGA Package) ..............................................45
BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package) ....................................................................................46
AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Core (For Both the S.E.P. and PPGA Packages)..............................47
AGTL+ Signal Groups Ringback Tolerance Specifications at
the Processor Pins (For FC-PGA Packages) .....................................................47
AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger
Measurement on the S.E.P. Package ................................................................48
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