參數(shù)資料
型號(hào)： celeron 700
廠商： Intel Corp.
英文描述： Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器)
中文描述： 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的）
文件頁數(shù)： 28/118頁
文件大?。?/td> 990K
代理商： CELERON 700
28
Datasheet
Intel
Celeron Processor up to 700 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. Parameter measured at 14 mA (for use with TTL inputs) for S.E.P Package and PPGA Package. It is 9 mA
for FC-PGA.
3. (0
≤
V
IN
≤
2.5 V +5%) for PPGA Package and S.E.P Package only.
4. (0
≤
V
OUT
≤
2.5 V +5%) for PPGA Package and S.E.P Package only.
5. (0
≤
V
IN
≤
1.5V +3%) for FC-PGA Package only.
6. (0
≤
V
OUT
≤
1.5V +3%) for FC-PGA Package only.
7. Applies to non-AGTL+ signals BCLK, PICCLK, and PWRGOOD for FC-PGA Package only.
8. Applies to non-AGTL+ signals
except
BCLK, PICCLK, and PWRGOOD for FC-PGA Package only.
9. These values are specified at the processor pins for FC-PGA Package only.
10.S.E.P. Package and PPGA Package only.
2.11
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to V
TT
at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the V
TT
voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called V
REF
. Single ended termination may be possible if trace
lengths are tightly controlled, see the
Intel
440EX AGPset Design Guide
(Order Number 290637)
or the
Intel
Celeron
Processor (PPGA) with the Intel
440LX AGPset Design Guide
(Order
Number 245088) for more information.
Table 8
below lists the nominal specification for the AGTL+ termination voltage (V
TT
). The
AGTL+ reference voltage (V
REF
) is generated on the processor substrate (S.E.P. Package only) for
the processor core, but should be set to
2
/
3
V
TT
for other AGTL+ logic using a voltage divider on
the motherboard. It is important that the motherboard impedance be specified and held to:
±20% tolerance (S.E.E.P. and PPGA)
±15% tolerance (FC-PGA)
Table 7. Non-AGTL+ Signal Group DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
V
IL
Input Low Voltage
–0.3
0.7
V
10
V
IH
Input High Voltage
1.7
2.625
V
2.5 V +5% maximum,
Note 10
V
IL
1.5
Input Low Voltage
–0.150
V
REF
- 0.200
V
8, 9
V
IL
2.5
Input Low Voltage
-0.58
0.700
V
7, 9
V
IH
1.5
Input High Voltage
V
REF
+ 0.200
V
TT
V
5, 8, 9
V
IH
2.5
Input High Voltage
2.0
3.18
V
7, 9
V
OL
Output Low Voltage
0.4
V
2
V
OH
Output High Voltage
S.E.P.P and PPGA
N/A
2.625
V
All outputs are open-
drain to 2.5 V +5%
FC-PGA
V
TT
V
6, 8, 9
I
OL
Output Low Current
S.E.P.P and PPGA
14
mA
FC-PGA
9
mA
9
I
L
Leakage Current for
Inputs, Outputs, and I/O
±100
μA
3, 4, 5, 6
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