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| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁(yè)數(shù)： | 57/118頁(yè) |
| 文件大小： | 990K |
| 代理商： | CELERON 700 |
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Datasheet
57
Intel
Celeron Processor up to 700 MHz
NOTES:
1. These values are specified at nominal V
CCCORE
for the processor core.
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tjunction specification.
3. FC-PGA package only
4.
The Thermal Design Power (TDP) Celeron processors in production has been redefined. The updated
TDP values are based on device characterization and do not reflect any silicon design changes to lower
processor power consumption. The TDP values represent the thermal design point required to cool
Celeron processors in the platform environment while executing thermal validation type software.
5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the
die area over which the power is generated. Power for these processors is generated from the core area
shown in
Figure 16
.
6. T
is the worst-case difference between the thermal reading from the on-die thermal diode and the
hottest location on the processor’s core. T
values do not include any thermal diode kit
measurement error. Diode kit measurement error must be added to the T
value from the table.
Intel has characterized the use of the Analog Devices AD1021 diode measurement kit and found its
measurement error to be ±1
o
C
Figure 16
is a block diagram of the Intel Celeron FC-PGA processor die layout. The layout
differentiates the processor core from the cache die area. In effect, the thermal design power
identified in
Table 37
is dissipated entirely from the processor core area. Thermal solution designs
should compensate for this smaller heat flux area and not assume that the power is uniformly
distributed across the entire die area.
Table 37. Processor Power for the PPGA and FC-PGA Packages
1
Processor
Core
Frequency
(MHz)
L2 Cache
Size
(KB)
Thermal
Design
Power
(TDP)
2
(W)
Power
Density
5
(W/cm
2
)
Up to
CPUID
0683h
Power
Density
5
(W/cm
2
)
For
CPUID
0686h
Heat Sink
Design
Target (W)
Min T
CASE
(°C)
Max T
CASE
(°C)
Max
T
JUNCTION
T
Offset
6
(°C)
300A
128
17.8
NA
NA
17.8
5
85
NA
NA
333
128
19.7
NA
NA
19.7
5
85
NA
NA
366
128
21.7
NA
NA
21.7
5
85
NA
NA
400
128
23.7
NA
NA
23.7
5
85
NA
NA
433
128
24.1
NA
NA
24.1
5
85
NA
NA
466
128
25.6
NA
NA
25.6
5
70
NA
NA
500
128
27.0
NA
NA
27.0
5
70
NA
NA
533
533A
3
566
3
600
3
128
28.3
11.2
4
11.9
4
12.6
4
16.5
4
17.5
4
18.3
4
NA
15.4
4
16.4
4
17.4
4
22.7
4
24.1
4
25.2
4
NA
17.5
4
18.5
4
19.7
4
25.8
4
27.3
4
28.6
4
28.3
11.2
4
11.9
4
12.6
4
16.5
4
17.5
4
18.3
4
5
70
NA
NA
128
NA
NA
90
2.5
128
NA
NA
90
2.6
128
NA
NA
90
2.6
633
128
NA
NA
82
2.6
667
128
NA
NA
82
2.6
700
128
NA
NA
80
2.6
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