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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁(yè)數(shù)： | 116/118頁(yè) |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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116
Datasheet
Intel
Celeron Processor up to 700 MHz
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and may latch interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units, resumes execution, and services
any pending interrupt. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor
Test Access Port.
TDI
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI
(S.E.P.P. only)
I
Refer to
Section 2.6
for implementation details.
THERMDN
O
Thermal Diode p-n junction. Used to calculate core temperature. See
Section 4.1
.
THERMDP
I
Thermal Diode p-n junction. Used to calculate core temperature. See
Section 4.1
.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched,
and the processor stopped, until RESET# goes active. There is no hysteresis built
into the thermal sensor itself; as long as the die temperature drops below the trip
level, a RESET# pulse will reset the processor and execution will continue. If the
temperature has not dropped below the trip level, the processor will reassert
THERMTRIP# and remain stopped.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel
Celeron processors require this signal to be driven low during power on Reset. A
680 ohm resistor is the suggested value for a pull down resistor on TRST#.
V
CC1.5
(PGA packages
only)
I
The V
CCCMOS
pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the V
CC2.5
input and 1.5 V must be provided to the V
CC1.5
input.
The processor re-routes the 1.5 V input to the V
CCCMOS
output via the package. The
supply for V
CC1.5
must be the same one used to supply V
TT.
V
CC2.5
(PGA packages
only)
I
The V
CCCMOS
pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the V
CC2.5
input and 1.5 V must be provided to the V
CC1.5
input.
The processor re-routes the 2.5 V input to the V
CCCMOS
output via the package.
V
CCCMOS
(PGA packages
only)
O
The V
CCCMOS
pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the V
CC2.5
input and 1.5 V must be provided to the V
CC1.5
input.
V
COREDET
(PGA packages
only)
O
The V
COREDET
signal will float for 2.0 V core processors and will be grounded for
Celeron FC-PGA processor with a 1.5V core voltage.
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
O
The VID (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
SS
on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See
Table 2
for
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
Table 54. Alphabetical Signal Reference (Sheet 6 of 7)
Signal
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| celeron cpu Mobile Module | processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器) |
| celeron CPU with Mobile Module | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| Celeron Processor with mobile | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器1處理器) |
| celeron processor | 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CELF001001J1 | 制造商:Panasonic Industrial Company 功能描述:FILTER |
| CELHK11-1REC5-59-3.00-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 3A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:3A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動(dòng)器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-59-35.0-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 35A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:35A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動(dòng)器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-10-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-11-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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