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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁數(shù)： | 34/118頁 |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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34
Datasheet
Intel
Celeron Processor up to 700 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processors at all
frequencies and cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50
to 1.5V and with V
REF
at 1.0 V.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from V
REF
- 200 mV to V
REF
+ 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 1.0 V swing from V
TT
- 1V to V
TT
. This assumes an edge rate of 3V/ns.
9. This should be measured after V
CCCORE
, V
CCCMOS
, and BCLK become stable.
10.This specification applies to the FC-PGA running at 66 MHz system bus frequency.
1. Unless otherwise noted, all specifications in this table apply to all Intel Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.50 V at the processor edge
fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an
edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.
PWRGOOD must remain below V
(
Table 6
) until all the voltage planes meet the voltage tolerance
specifications in
Table 5
and BCLK has met the BCLK AC specifications in
Table 10
for at least 10 clock
cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
6. When driven inactive or after V
CCCORE
, and BCLK become stable.
7. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse
width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still
remain below V
IL,max
until all the voltage planes meet the voltage tolerance specifications.
Table 15. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
(for FC-PGA Package)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.40
3.25
ns
4
4, 10
T8: AGTL+ Input Setup Time
1.20
ns
5
5, 6, 7, 10
T9: AGTL+ Input Hold Time
1.00
ns
5
8, 10
T10: RESET# Pulse Width
1.00
ms
7
6, 9, 10
Table 16. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers
(for S.E.P. Package)
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14’: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
8
Active and
Inactive states
T14B: LINT[1:0] Input Pulse Width
6
BCLKs
8
5
T15’: PWRGOOD Inactive Pulse Width
10
BCLKs
8
6, 7
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