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參數(shù)資料
| 型號： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁數(shù)： | 47/118頁 |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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Datasheet
47
Intel
Celeron Processor up to 700 MHz
3.2
AGTL+ Signal Quality Specifications and Measurement
Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in AP-585,
Pentium
II Processor AGTL+ Guidelines
(Order Number 243330). Refer to
the
Pentium
II Processor Developer’s Manual
(Order Number 243502) for the AGTL+ buffer
specification.
Table 27
provides the AGTL+ signal quality specifications (for both the S.E.P. and PPGA
Packages) for use in simulating signal quality at the processor core.
Table 28
provides the AGTL+
signal quality specifications (for the FC-PGA Packages) for use in simulating signal quality at the
processor core.
Table 29
provides AGTL+ signal quality guidelines for measuring and testing
signal quality at the processor edge fingers.
Figure 13
describes the signal quality waveform for
AGTL+ signals at the processor core and edge fingers. For more information on the AGTL+
interface, see the
Pentium
II Processor Developer’s Manual
(Order Number 243502).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8 V/ns. See
Figure 13
for the generic waveform.
3. All values specified by design characterization.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Ringback below V
REF
+ 20 mV is not supported.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron
processor frequencies.
2. Specifications are for the edge rate of 0.3 - 0.8V/ns. See
Figure 13
for the generic waveform.
3. All values specified by design characterization.
4. See
Table 32
for maximum allowable overshoot.
5. Ringback between V
REF
+ 100 mV and V
REF
+ 200 mV or V
REF
- 200 mV and V
REF
- 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (
Intel
Pentium
II
Developers Manual). Ringback below V
REF
+ 100 mV or above V
REF
- 100 mV is not supported.
6. Intel recommends simulations not exceed a ringback value of V
REF
±200 mV to allow margin for other
sources of system noise.
7. A negative value for
ρ
indicates that the amplitude of ringback is above V
REF
. (i.e.,
φ
= -100 mV specifies the
signal cannot ringback below V
REF
+ 100 mV).
8.
φ
and
ρ
: are measured relative to V
REF
.
α
: is measured relative to V
REF
+ 200 mV.
9. All Ringback entering the Overdrive Region must have flight time correction.
10.Overshoot specifications for Ringback do not correspond to Overshoot specifications in
Section 3.4
.
Table 27. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core
(For Both the S.E.P. and PPGA Packages)
1, 2, 3
T# Parameter
Min
Unit
Figure
Notes
α
: Overshoot
τ
: Minimum Time at High
ρ
: Amplitude of Ringback
φ
: Final Settling Voltage
δ
: Duration of Squarewave Ringback
100
mV
13
4
1.00
ns
13
4
–100
mV
13
4, 5
100
mV
13
4
N/A
ns
13
Table 28. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins
(For FC-PGA Packages)
1, 2, 3
T# Parameter
Min
Unit
Figure
Notes
α
: Overshoot
τ
: Minimum Time at High
ρ
: Amplitude of Ringback
φ
: Final Settling Voltage
δ
: Duration of Squarewave Ringback
100
mV
13
4, 8, 9, 10
0.50
ns
13
9
–200
mV
13
5, 6, 7, 8
200
mV
13
8
N/A
ns
13
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