
Datasheet
3
Intel
Celeron Processor up to 700 MHz
Contents
1.0
Introduction.........................................................................................................................9
1.1
Terminology...........................................................................................................9
1.1.1
Package Terminology.............................................................................10
1.1.2
Processor Naming Convention...............................................................11
1.2
References..........................................................................................................12
2.0
Electrical Specifications....................................................................................................13
2.1
System Bus and Vref...........................................................................................13
2.2
Clock Control and Low Power States..................................................................13
2.2.1
Normal State—State 1 ...........................................................................14
2.2.2
AutoHALT Power Down State—State 2.................................................14
2.2.3
Stop-Grant State—State 3 .....................................................................15
2.2.4
HALT/Grant Snoop State—State 4 ........................................................15
2.2.5
Sleep State—State 5..............................................................................15
2.2.6
Deep Sleep State—State 6 ....................................................................16
2.2.7
Clock Control..........................................................................................16
2.3
Power and Ground Pins......................................................................................16
2.3.1
Phase Lock Loop (PLL) Power...............................................................17
2.4
Processor Decoupling.........................................................................................17
2.4.1
System Bus AGTL+ Decoupling.............................................................17
2.5
Voltage Identification...........................................................................................17
2.6
System Bus Unused Pins....................................................................................19
2.7
Processor System Bus Signal Groups................................................................19
2.7.1
Asynchronous Vs. Synchronous for System Bus Signals ......................21
2.7.2
System Bus Frequency Select Signal (BSEL[1:0]).................................21
2.8
Test Access Port (TAP) Connection....................................................................21
2.9
Maximum Ratings................................................................................................21
2.10
Processor DC Specifications...............................................................................22
2.11
AGTL+ System Bus Specifications .....................................................................28
2.12
System Bus AC Specifications............................................................................29
3.0
System Bus Signal Simulations........................................................................................44
3.1
System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines ....................................................................................44
3.2
AGTL+ Signal Quality Specifications and Measurement Guidelines ..................47
3.3
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........49
3.3.1
Overshoot/Undershoot Guidelines.........................................................49
3.3.2
Ringback Specification...........................................................................50
3.3.3
Settling Limit Guideline...........................................................................51
3.4
AGTL+ Signal Quality Specifications and Measurement
Guidelines (FC-PGA Package) ...........................................................................51
3.4.1
Overshoot/Undershoot Guidelines (FC-PGA Package) .........................51
3.4.2
Overshoot/Undershoot Magnitude (FC-PGA Package) .........................51
3.4.3
Overshoot/Undershoot Pulse Duration (FC-PGA Package)...................52
3.4.4
Activity Factor (FC-PGA Package).........................................................52
3.4.5
Reading Overshoot/Undershoot Specification
Tables (FC-PGA Package).....................................................................53