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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁數(shù)： | 29/118頁 |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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Datasheet
29
Intel
Celeron Processor up to 700 MHz
It is also important that the intrinsic trace capacitance for the AGTL+ signal group traces is known
and well-controlled. For more details on AGTL+, see the
Pentium
II Processor Developer’s
Manual
(Order Number 243502) and AP-585,
Pentium
II Processor AGTL+ Guidelines
(Order
Number 243330).
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. V
TT
must be held to 1.5 V ± 9%; dI
CC
/dt is specified in
Table 5
. It is recommended that V
TT
be held to
1.5 V ± 3% while the Intel Celeron processor system bus is idle. This is measured at the processor edge
fingers.
3. V
REF
is generated on the processor substrate to be
2
/
V
TT
nominally with the S.E.P. package. It must be
created on the motherboard for processors in the PPGA package.
4. V
and Vcc
must be held to 1.5V ±9%. It is required that V
and Vcc
be held to 1.5V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
5. The value of the on-die R
is determined by the resistor value measured by the RTTCTRL signal pin. The
on-die R
tolerance is ±15% based on the RTTCTRL resistor pull-down of ±1%. See
Section 7.0
for more
details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific chipset/processor
combination.
6. V
REF
is generated on the motherboard and should be 2/3 V
TT
±2% nominally. Insure that there is adequate
V
REF
decoupling on the motherboard.
2.12
System Bus AC Specifications
The Intel
Celeron
processor system bus timings specified in this section are defined at the Intel
Celeron processor edge fingers and the processor core pins. Timings specified at the processor
edge fingers only apply to the S.E.P. Package and timings given at the processor core pins apply to
all S.E.P. Package and PGA packages. Unless otherwise specified, timings are tested at the
processor core during manufacturing. Timings at the processor edge fingers are specified by design
characterization. See
Section 7.0
for the Intel Celeron processor signal definitions.
Note that at 66
MHz system bus operation, the Intel Celeron processor timings at the processor edge fingers
are identical to the Pentium II processor timings at the edge fingers.
See the
Pentium
II
Processor at 233, 266, 300, and 333 MHz
(Order Number 243335) for more detail.
Table 9
through
Table 23
list the AC specifications associated with the Intel Celeron processor
system bus. These specifications are broken into the following categories:
Table 9
through
Table
11
contain the system bus clock specifications,
Table 12
and
Table 13
contain the AGTL+
specifications,
Table 16
and
Table 17
are the CMOS signal group specifications,
Table 18
contains
timings for the Reset conditions,
Table 20
and
Table 21
cover APIC bus timing, and
Table 22
and
Table 8. Processor AGTL+ Bus Specifications
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
TT
Bus Termination Voltage
S.E.P.P and PPGA
1.365
1.50
1.635
V
1.5 V ± 9%
2
FC-PGA
1.50
V
4
R
TT
Termination Resistor
S.E.P.P and PPGA
56
± 5%
FC-PGA (on die R
TT
)
40
130
5
V
REF
Bus Reference Voltage
S.E.P.P and PPGA
2
/
3
V
TT
V
± 2%
3
FC-PGA
0.950
2/3 V
TT
1.05
V
6
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