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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁(yè)數(shù)： | 49/118頁(yè) |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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Datasheet
49
Intel
Celeron Processor up to 700 MHz
3.3
Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in
Figure 14
for the non-
AGTL+ signal group.
NOTES:
1. For the FC-PGA package, V
= 1.5V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD.
V
HI
= 2.5 V for BCLK, PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in
Section 3.1
.
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below V
SS
. The overshoot/undershoot guideline limits transitions beyond V
CC
or V
SS
due to the fast signal edge rates. (See
Figure 14
for non-AGTL+ signals.) The processor can be
damaged by repeated overshoot events on the voltage tolerant buffers if the charge is large enough
(i.e., if the overshoot is great enough). The PPGA and S.E.P. packages have 2.5V tolerant buffers
and the FC-PGA package has 1.5V or 2.5V tolerant buffers.
However, excessive ringback is the dominant detrimental system timing effect resulting from
overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the
ringback specification difficult).
The overshoot/undershoot guideline is 0.7 V for the PPGA
and S.E.P. packages and 0.3 V for the FC-PGA package
and assumes the absence of diodes on
the input. These guidelines should be verified in simulations
without the on-chip ESD protection
diodes present
because the diodes will begin clamping the signals (2.5 V tolerant signals for the
S.E.P. and PPGA packages, and 2.5 V or 1.5 V tolerant signals for the FC-PGA package)
beginning at approximately 0.7 V above the appropriate supply and 0.7 V below V
SS
. If signals are
not reaching the clamping voltage, this will not be an issue. A system should not rely on the diodes
for overshoot/undershoot protection as this will negatively affect the life of the components and
make meeting the ringback specification very difficult.
Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
Undershoot
Overshoot
Settling Limit
Settling Limit
Rising-Edge
Ringback
Falling-Edge
Ringback
V
LO
V
SS
Time
V
HI
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