
Datasheet
5
Intel
Celeron Processor up to 700 MHz
Figures
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Clock Control State Machine...............................................................................14
BCLK to Core Logic Offset..................................................................................40
BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................40
System Bus Valid Delay Timings ........................................................................41
System Bus Setup and Hold Timings..................................................................41
System Bus Reset and Configuration Timings
(For the S.E.P. and PPGA Packages).................................................................41
System Bus Reset and Configuration Timings (For the FC-PGA Package) .......42
Power-On Reset and Configuration Timings.......................................................42
Test Timings (TAP Connection)..........................................................................43
Test Reset Timings .............................................................................................43
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....45
BCLK, TCK, PICCLK Generic Clock Waveform at the
Processor Edge Fingers......................................................................................46
Low to High AGTL+ Receiver Ringback Tolerance.............................................48
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................49
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA Package) .............................................................................................55
Processor Functional Die Layout ........................................................................58
Processor Substrate Dimensions (S.E.P. Package) ...........................................61
Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....61
Package Dimensions (PPGA Package)..............................................................70
PPGA Package (Pin Side View)..........................................................................72
Package Dimensions (FC-PGA Package)...........................................................83
Top Side Processor Markings (PPGA and FC-PGA Packages) .........................85
Package Dimensions (FC-PGA Package)...........................................................86
Retention Mechanism for the Boxed Intel Celeron
Processor in the S.E.P. Package......................................................................100
Side View Space Requirements for the Boxed Processor
in the S.E.P. Package .......................................................................................100
Front View Space Requirements for the Boxed Processor
the S.E.P. Package...........................................................................................101
Boxed Intel Celeron Processor in the PPGA Package................................102
Side View Space Requirements for the Boxed Processor
in the PPGA Package........................................................................................102
Top View Space Requirements for the Boxed Processor in
the FC-PGA and PPGA Packages....................................................................103
Side View Space Requirements for the Boxed Processor
‘in the FC-PGA and PPGA Packages ...............................................................103
Boxed Intel
Celeron processor in the 370-pin socket (FC-PGA Package) ..105
Dimensions of Notches in Heatsink Base .........................................................105
Dimensions of Mechanical Step Feature in Heatsink
Base for the FC-PGA Package .........................................................................106
Top View Airspace Requirements for the Boxed Processor
in the S.E.P. Package .......................................................................................107
Side View Airspace Requirements for the Boxed Intel Celeron
Processor in the FC-PGA and PPGA packages ...............................................107
Clip Keepout Requirements for the 370-Pin (Top View) ...................................108
Boxed Processor Fan Heatsink Power Cable Connector Description...............109
Motherboard Power Header Placement for the S.E.P. Package.......................109
Motherboard Power Header Placement Relative to the 370-pin Socket...........110
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