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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁(yè)數(shù)： | 17/118頁(yè) |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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Datasheet
17
Intel
Celeron Processor up to 700 MHz
The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the
power pins, 77 are used for the processor core (V
CCCORE
) and 8 are used as a AGTL+ reference
voltage (V
REF
). The other 3 power pins are V
CC1.5
, V
CC2.5
and V
CCCMOS
and are used for future
processor compatibility.
FC-PGA package has 77 V
CCCORE
, 77 ground pins, eight V
REF
, one V
CC1.5
, one V
CC2.5
, and one
V
CCCMOS
. V
CCCORE
inputs supply the processor core, including the on-die L2 cache. The V
REF
inputs are used as the AGTL+ reference voltage for the processor.
The V
CCCMOS
pin is provided as a feature for future processor support in a flexible design. In such
a design, the V
CCCMOS
pin is used to provide the CMOS voltage for use by the platform.
Additionally, 2.5 V must be provided to the V
CC2.5
input and 1.5 V must be provided to the Vcc
1.5
input. The processor routes the CMOS voltage level through the package that it is compatible with.
For example, processors requiring 1.5 V CMOS voltage levels route 1.5 V to the V
CCCMOS
output.
Each power signal, regardless of package, must meet the specifications stated in
Table 4
. In
addition, all V
CCCORE
pins must be connected to a voltage island while all V
SS
pins have to
connect to a system ground plane. In addition, the motherboard must implement the V
TT
pins as a
voltage island or large trace. Similarly, all V
SS
pins must be connected to a system ground plane.
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL.
2.4
Processor Decoupling
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in
Table 5
. Failure to do so can result in timing violations or a reduced lifetime
of the component.
2.4.1
System Bus AGTL+ Decoupling
The S.E.P. Package and FC-PGA package contain high frequency decoupling capacitance on the
processor substrate, where the PPGA package does not. Therefore, Intel
Celeron processors in
the PGA packages require high frequency decoupling on the system motherboard. Bulk decoupling
must be provided on the motherboard for proper AGTL+ bus operation for all packages. See AP-
585,
Pentium
II Processor AGTL+ Guidelines
(Order Number 243330), AP-587,
Pentium
II
Processor Power Distribution Guidelines
(Order Number 243332), and the
Pentium
II Processor
Developer’s Manual
(Order Number 243502) for more information.
2.5
Voltage Identification
The processor’s voltage identification (VID) pins can be used to automatically select the V
CCCORE
voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P.
Package, while there are only four (VID[3:0]) on the PGA packages. This is because there are no
Intel
Celeron processors in the PGA package that require more than 2.05 V (see
Table 2
).
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