參數(shù)資料
型號(hào)： celeron 700
廠商： Intel Corp.
英文描述： Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器)
中文描述： 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的）
文件頁數(shù)： 111/118頁
文件大小： 990K
代理商： CELERON 700
Datasheet
111
Intel
Celeron Processor up to 700 MHz
7.0
Intel
Celeron Processor Signal Description
Table 54
provides an alphabetical listing of all Intel
Celeron processor signals. The tables at the
end of this section summarize the signals by direction: output, input, and I/O.
Note:
Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA Packages.
Table 54. Alphabetical Signal Reference (Sheet 1 of 7)
Signal
Type
Description
A[31:3]#
I/O
The A[31:3]# (Address) signals define a 2
32
-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type infor Celeron processor system
connect the appropriate pins of all agents on the Intel
bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the
A[23:3]# signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]#
pins to determine their power-on configuration. See the
Pentium
II Processor
Developer’s Manual
(Order Number 243502) for details.
A20M#
I
If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron
processor masks physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor’s address wrap-around at the 1 MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS#
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[31:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system
bus agents.
BCLK
I
The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron
processor system bus agents must receive this signal to drive their outputs and latch
their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
BNR#
I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all Intel Celeron
processor system bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BNR# is activated on
specific clock edges and sampled on specific clock edges.
BP[3:2]#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
BPM[1:0]#
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
BPRI#
I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
Intel Celeron processor system bus. It must connect the appropriate pins of all Intel
Celeron processor system bus agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed, then releases the bus by deasserting
BPRI#.
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