參數(shù)資料
型號： celeron 700
廠商： Intel Corp.
英文描述： Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器)
中文描述： 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的）
文件頁數(shù)： 35/118頁
文件大?。?/td> 990K
代理商： CELERON 700
Datasheet
35
Intel
Celeron Processor up to 700 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pins. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an
edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.
6. When driven inactive or after V
CCCORE
, and BCLK become stable.
7. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse
width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still
remain below V
IL,max
until all the voltage planes meet the voltage tolerance specifications.
PWRGOOD must remain below V
(
Table 6
) until all the voltage planes meet the voltage tolerance
specifications in
Table 5
and BCLK has met the BCLK AC specifications in
Table 10
for at least 10 clock
cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
1. Unless otherwise noted, all specifications in this table apply to all Intel Celeron processor frequencies.
Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins
(for Both S.E.P. and PGA Packages)
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
8
Active and
Inactive states
T14B: LINT[1:0] Input Pulse Width
(S.E.P.P. Only)
6
BCLKs
8
5
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
8
6, 7
Table 18. System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages)
1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Setup Time
4
BCLKs
6
Before deassertion
of RESET#
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
2
20
BCLKs
6
After clock that
deasserts RESET#
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