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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁數(shù)： | 113/118頁 |
| 文件大?。?/td> | 990K |
| 代理商： | CELERON 700 |
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Datasheet
113
Intel
Celeron Processor up to 700 MHz
EMI
(S.E.P.P. only)
I
EMI pins should be connected to motherboard ground and/or to chassis ground
through zero ohm (0
) resistors. The zero ohm resistors should be placed in close
proximity to the Intel Celeron processor connector. The path to chassis ground
should be short in length and have a low impedance. These pins are used for EMI
management purposes.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting.
FLUSH#
I
When the FLUSH# input signal is asserted, the processor writes back all data in the
Modified state from the internal cache and invalidates all internal cache lines. At the
completion of this operation, the processor issues a Flush Acknowledge transaction.
The processor does not cache any new data while the FLUSH# signal remains
asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, the processor samples FLUSH# to
determine its power-on configuration. See Pentium
Pro Family Developer’s
Manual, Volume 1: Specifications
(Order Number 242690) for details.
HIT#, HITM#
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all Intel Celeron
processor system bus agents. Any such agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be continued by
reasserting HIT# and HITM# together.
IERR#
O
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the Intel Celeron processor system bus. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.
IGNNE#
I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point instructions.
If IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
INIT#
I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1) caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal and must connect the
appropriate pins of all bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
LINT[1:0]
I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Pentium
processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
Table 54. Alphabetical Signal Reference (Sheet 3 of 7)
Signal
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| celeron cpu Mobile Module | processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器) |
| celeron CPU with Mobile Module | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| Celeron Processor with mobile | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動(dòng)模塊和連接器1處理器) |
| celeron processor | 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CELF001001J1 | 制造商:Panasonic Industrial Company 功能描述:FILTER |
| CELHK11-1REC5-59-3.00-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 3A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:3A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動(dòng)器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-59-35.0-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 35A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:35A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動(dòng)器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-10-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-11-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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