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參數(shù)資料
| 型號： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚處理器高達700兆赫（頻率達700MHz的英特爾賽揚處理器的） |
| 文件頁數(shù)： | 13/118頁 |
| 文件大小： | 990K |
| 代理商： | CELERON 700 |
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Datasheet
13
Intel
Celeron Processor up to 700 MHz
2.0
Electrical Specifications
2.1
System Bus and V
REF
Intel
Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology. The Intel
Celeron processor system bus specification is similar to the
GTL specification, but has been enhanced to provide larger noise margins and reduced ringing.
The improvements are accomplished by increasing the termination voltage level and controlling
the edge rates. Because this specification is different from the standard GTL specification, it is
referred to as Assisted Gunning Transceiver Logic (AGTL+) in this document.
The Intel
Celeron processor varies from the Pentium Pro processor in its output buffer
implementation. The buffers that drive the system bus signals on the Intel
Celeron processor are
actively driven to V
CCCORE
for one clock cycle during the low-to-high transition. This improves
rise times and reduces overshoot. These signals should still be considered open-drain and require
termination to a supply that provides the logic-high signal level.
The AGTL+ inputs use differential receivers which require a reference signal (V
REF
). V
REF
is used
by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the
processor core by either the processor substrate (S.E.P. Package) or the motherboard (PGA370
socket). Local V
REF
copies should be generated on the motherboard for all other devices on the
AGTL+ system bus.
Termination is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor may contain termination resistors (S.E.P. Package and FC-PGA
Package) that provide termination for one end of the Intel Celeron processor system bus.
Otherwise, this termination must exist on the motherboard.
Solutions exist for single-ended termination as well, though this implementation changes system
design and eliminate backwards compatibility for Intel
Celeron processors in the PPGA
package. Single-ended termination designs must still provide an AGTL+ termination resistor on
the motherboard for the RESET# signal.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on motherboard
flight time
as opposed to capacitive deratings. Analog signal
simulation of the Intel Celeron processor system bus, including trace lengths, is highly
recommended when designing a system. See the
Pentium
II Processor AGTL+ Layout Guidelines
and the
Pentium
II Processor I/O Buffer Models, Quad Format
(Electronic Form) for details.
2.2
Clock Control and Low Power States
Intel
Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to
reduce power consumption by stopping the clock to internal sections of the processor, depending
on each particular state. See
Figure 1
for a visual representation of the Intel Celeron processor low
power states.
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the
Pentium
II Processor Developer’s Manual
(Order Number 243502).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| celeron cpu Mobile Module | processor Mobile Module Connector 1 (MMC-1) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器1處理器) |
| celeron CPU with Mobile Module | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| Celeron Processor with mobile | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器1處理器) |
| celeron processor | 32 bit Celeron Processor Mobile Module(32 位帶移動模塊處理器) |
| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CELF001001J1 | 制造商:Panasonic Industrial Company 功能描述:FILTER |
| CELHK11-1REC5-59-3.00-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 3A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:3A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-59-35.0-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 35A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:35A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-10-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-11-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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