參數(shù)資料
型號(hào)： celeron 700
廠商： Intel Corp.
英文描述： Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器)
中文描述： 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的）
文件頁數(shù)： 27/118頁
文件大?。?/td> 990K
代理商： CELERON 700
Datasheet
27
Intel
Celeron Processor up to 700 MHz
7. These are the tolerance requirements, across a 20 MHz bandwidth,
at the processor edge fingers.
The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. V
CCCORE
must return to within the static voltage
specification within 100
μ
s after a transient event.
8. These are the tolerance requirements, across a 20 MHz bandwidth,
at the top of the PPGA package.
V
CCCORE
must return to within the static voltage specification within 100
μ
s after a transient event.
9. Max I
CC
measurements are measured at V
CCCORE
max voltage (V
CCCORE_TYP
+ maximum static
tolerance), under maximum signal loading conditions.
10.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of V
CCCORE
(V
CCCORE_TYP
). In this case, the maximum current level for the regulator, I
CCCORE_REG
, can be reduced from
the specified maximum current I
CC
CORE_MAX
and is calculated by the equation:
I
CC
= I
CC
×
V
CCCORE_TYP
/ (V
CCCORE_TYP
+ V
CCCORE
Tolerance, Transient)
11.The current specified is the current required for a single Intel Celeron processor. A similar amount of current
is drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended
termination is used (see
Section 2.1
).
12.The current specified is also for AutoHALT state.
13.Maximum values are specified by design/characterization at nominal V
CCCORE
.
14.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
15.dI
CC
/dt specifications are measured and specified at the SC242 connector pins.
16.FC-PGA only
17.These are the tolerance requirements across a 20 MHz bandwidth at the FC-PGA socket pins on the solder
side of the motherboard. V
CCCORE
must return to within the static voltage specification within 100
μ
s after a
transient event.
18.PGA only
19.S.E.P Package and FC-PGA Packages only.
20.These processors implement independent V
TT
and V
CCCORE
power planes.
Table 6. AGTL+ Signal Groups DC Specifications
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies and
cache sizes.
2. V
and V
for the Intel Celeron processor may experience excursions of up to 200 mV above V
TT
for a
single system bus clock. However, input signal drivers must comply with the signal quality specifications in
Section 3.0
.
3. Minimum and maximum V
TT
are given in
Table 8
.
4. Parameter correlated to measurement into a 25
resistor terminated to 1.5 V.
5. I
OH
for the Intel Celeron processor may experience excursions of up to 12 mA for a single system bus clock.
6. (0
≤
V
IN
≤
2.0 V +5%) for S.E.P Package and PPGA Package; (0
≤
V
IN
≤
1.5V +3%) for FC-PGA package.
7. (0
≤
V
OUT
≤
2.0 V +5%) for S.E.P Package and PPGA Package; (0
≤
V
OUT
≤
1.5V +3%) for FC-PGA
package.
8. Refer to the I/O Buffer Models for IV characteristics.
9. Steady state input voltage must not be above V
SS
+ 1.65V or below V
TT
- 1.65V.
Symbol
Parameter
Min
Max
Unit
Notes
V
IL
Input Low Voltage
S.E.P.P and PPGA
–0.3
0.82
V
FC-PGA
–0.150
V
REF
- 0.200
V
9
V
IH
Input High Voltage
S.E.P.P and PPGA
1.22
V
TT
V
2, 3
FC-PGA
V
REF
+ 0.200
V
TT
V
2, 3
R
ON
Buffer On Resistance
16.67
8
I
L
Leakage Current for
inputs, outputs, and I/O
±100
μA
6, 7
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