參數(shù)資料
型號: celeron 700
廠商: Intel Corp.
英文描述: Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器)
中文描述: 英特爾賽揚(yáng)處理器高達(dá)700兆赫(頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的)
文件頁數(shù): 20/118頁
文件大?。?/td> 990K
代理商: CELERON 700
20
Datasheet
Intel
Celeron Processor up to 700 MHz
open drain and should be pulled high to V
CCCMOS
. This ensures not only correct operation for
current Intel Celeron processors, but compatibility for future Intel Celeron processor products as
well.
The groups and the signals contained within each group are shown in
Table 3
. Refer to
Section 7.0
for descriptions of these signals.
NOTES:
1. See
Section 7.0
for information on the PWRGOOD signal.
2. See
Section 7.0
for information on the SLP# signal.
3. See
Section 7.0
for information on the THERMTRIP# signal.
4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V
operation for the FC-PGA package
5. V
CCCORE
is the power supply for the processor core.
VID[4:0] and VID[3:0] are described in
Section 2.0
.
V
TT
is used to terminate the system bus and generate V
REF
on the processor substrate.
V
SS
is system ground.
V
CC5
is not connected to the Intel
Celeron processor. This supply is used for Voltage Transient Tools.
SLOTOCC# is described in
Section 7.0
.
BSEL is described in
Section 2.7.2
and
Section 7.0
.
EMI pins are described in
Section 7.0
.
V
CCL2
is a Pentium
II processor reserved signal provided to maintain compatibility with the Pentium
II
processor and may be left as a no-connect
for “Intel Celeron processor-only” designs.
6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA packages.
8. The BR0# pin is the only BREQ# signal that is bidirectional. See
Section 7.0
for more information.
9. These signals are specified for 2.5 V operation.
10.BSEL1 is not used in Celeron processors.
11.RESET# must always be terminated to V
TT
on the motherboard for PGA packages. On-die termination is not
provided for this signal on FC-PGA.
12.For the FC-PGA, this signal is used to control the value of the processor on-die termination resistance. Refer
to the specific platform design guide for the recommended pull-down resistor value.
13.Only applies to Intel Celeron processors in the FC-PGA Package.
14.S.E.P. Package and FC-PGA Package.
Table 3. Intel
Celeron Processor System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, DEFER#, RESET#
11
, RS[2:0]#, TRDY#
AGTL+ Output
PRDY#
A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#
8
, D[63:0]#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#,
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#
2
,
STPCLK#
PWRGOOD
1,9
FERR#, IERR#, THERMTRIP#
3
BCLK
9
PICCLK
9
AGTL+ I/O
CMOS Input
4
CMOS Input
CMOS Output
4
System Bus Clock
APIC Clock
APIC I/O
4
PICD[1:0]
TAP Input
4
TCK, TDI, TMS, TRST#
TAP Output
4
TDO
CPUPRES#
7
, EDGCTRL
7
, EMI
6
, PLL[2:1]
7
, SLOTOCC#
6
, THERMDP, THERMDN,
V
CC1.57
, V
CC2.57
, V
7
, V
CC56
, V
CCCMOS7
, V
CCCORE
, V
10
, VID[3:0]
7
,
VID[4:0]
6
, V
REF
[7:0]
, V
SS
, V
TT14
, RTTCTRL
12
, BSEL[1:0]
, SLEWCTRL
13
Power/Other
5
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