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參數(shù)資料
| 型號： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚處理器的） |
| 文件頁數(shù)： | 30/118頁 |
| 文件大小： | 990K |
| 代理商： | CELERON 700 |
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30
Datasheet
Intel
Celeron Processor up to 700 MHz
Table 23
cover TAP timing. For each pair of tables, the first table contains timing specifications for
measurement or simulation at the processor edge fingers. The second table contains specifications
for simulation at the processor core pads.
All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative
to the rising edge of the BCLK input. All AGTL+ timings are referenced to V
REF
for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the
Intel Celeron Processor I/O Buffer Models
, Quad XTK Format (Electronic
Form). AGTL+ layout guidelines are also available in AP-585,
Pentium
II Processor AGTL+
Guidelines
(Order Number 243330).
Care should be taken to read all notes associated with a particular timing parameter.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data
bus, etc.) are referenced at 1.00 V at the processor edge fingers.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility
signals, etc.) are referenced at 1.25 V at the processor edge fingers.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization.
Table 11
shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron
processor edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to
account for the delay between the SC242 connector and processor core. The positive offset ensures both the
processor core and the core logic receive the BCLK edge concurrently.
8. See
Section 3.1
for Intel Celeron processor system bus clock signal quality specifications.
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)
1, 2, 3
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
66.67
MHz
T1’: BCLK Period
15.0
ns
3
4, 5, 6
Absolute Value
7,8
T1B’: SC242 to Core Logic BCLK Offset
0.78
ns
3
T2’: BCLK Period Stability
± 300
ps
See
Table 10
@>2.0 V
6
@<0.5 V
6
(0.5 V–2.0 V)
6, 9
(2.0 V–0.5 V)
6, 9
T3’: BCLK High Time
4.44
ns
3
T4’: BCLK Low Time
4.44
ns
3
T5’: BCLK Rise Time
0.84
2.31
ns
3
T6’: BCLK Fall Time
0.84
2.31
ns
3
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