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參數(shù)資料
| 型號(hào)： | celeron 700 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器) |
| 中文描述： | 英特爾賽揚(yáng)處理器高達(dá)700兆赫（頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的） |
| 文件頁數(shù)： | 44/118頁 |
| 文件大小： | 990K |
| 代理商： | CELERON 700 |
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44
Datasheet
Intel
Celeron Processor up to 700 MHz
3.0
System Bus Signal Simulations
Signals driven on the Intel
Celeron processor system bus should meet signal quality
specifications to ensure that the components read data properly and to ensure that incoming signals
do not affect the long term reliability of the component. Specifications are provided for simulation
at the processor core; guidelines are provided for correlation to the processor edge fingers. These
edge finger guidelines are intended for use during testing and measurement of system signal
integrity. Violations of these guidelines are permitted, but if they occur, simulation of signal
quality at the processor core should be performed to ensure that no violations of signal quality
specifications occur. Meeting the specifications at the processor core in
Table 24
,
Table 27
, and
Table 30
ensures that signal quality effects will not adversely affect processor operation, but does
not necessarily guarantee that the guidelines in
Table 26
,
Table 29
, and
Table 31
will be met.
3.1
System Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines
Table 24
describes the BCLK signal quality specifications at the processor core for both S.E.P. and
PPGA Packages.
Table 25
shows the BCLK and PICCLK signal quality specifications at the
processor core for the FC-PGA package.
Table 26
describes guidelines for signal quality
measurement at the processor edge fingers.
Figure 11
describes the signal quality waveform for the
system bus clock at the processor core pins;
Figure 12
describes the signal quality waveform for
the system bus clock at the processor edge fingers.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot specification for 66 MHz
system bus operation.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
specification is an absolute value.
Table 24. BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages)
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK V
IL
0.5
V
11
V2: BCLK V
IH
2.0
V
11
2
V3: V
IN
Absolute Voltage Range
–0.7
3.5
V
11
2
V4: Rising Edge Ringback
1.7
V
11
3
V5: Falling Edge Ringback
0.7
V
11
3
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