參數(shù)資料
型號(hào): celeron 700
廠商: Intel Corp.
英文描述: Intel Celeron Processor Up To 700 MHz(頻率達(dá)700MHz的INTEL Celeron 處理器)
中文描述: 英特爾賽揚(yáng)處理器高達(dá)700兆赫(頻率達(dá)700MHz的英特爾賽揚(yáng)處理器的)
文件頁數(shù): 40/118頁
文件大?。?/td> 990K
代理商: CELERON 700
40
Datasheet
Intel
Celeron Processor up to 700 MHz
Note:
For
Figure 3
through
Figure 10
, the following apply:
1.
Figure 3
through
Figure 10
are to be used in conjunction with
Table 9
through
Table 23
.
2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the
processor edge fingers.
3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor core pins.
4. All AC timings for the CMOS signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the
processor edge fingers.
5. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the
PICCLK rising edge at: 0.7 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA
package. All APIC I/O signal timings are referenced at 1.25 V for S.E.P. and PPGA packages
and 0.75 V for the FC-PGA package at the processor edge fingers.
6. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK
rising edge at 0.70 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA package. All
TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V for S.E.P. and PPGA packages
and 0.75 V for the FC-PGA package at the processor edge fingers.
Figure 2. BCLK to Core Logic Offset
Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform
BCLK at
Edge Fingers
0.5V
BCLK at
Core Logic
1.25V
T1B’
Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V.
For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V.
For the FC-PGA package, TCK is referenced to V
REF
±200mV.
1.7V (2.0V*)
1.25V
0.7V (0.5V*)
t
r
t
p
t
f
t
h
t
l
CLK
T
r
T
f
T
h
T
l
T
p
= T5, pT25, T34 (Rise Time)
= T6, T26, T35 (Fall Time)
= T3, T23, T32 (High Time)
= T4, T24, T33 (Low Time)
= T1, T22, T31 (BLCK, TCK, PICCLK Period)
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