參數(shù)資料
型號: celeron 700
廠商: Intel Corp.
英文描述: Intel Celeron Processor Up To 700 MHz(頻率達700MHz的INTEL Celeron 處理器)
中文描述: 英特爾賽揚處理器高達700兆赫(頻率達700MHz的英特爾賽揚處理器的)
文件頁數(shù): 38/118頁
文件大小: 990K
代理商: CELERON 700
38
Datasheet
Intel
Celeron Processor up to 700 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel
Celeron processor frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge
fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.
3. Not 100% tested. Specified by design characterization.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
Table 22. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers
(For S.E.P. Package)
1, 2, 3, 4, 5
T# Parameter
Min
Max
Unit
Figure
Notes
T30’: TCK Frequency
16.667
MHz
T31’: TCK Period
60.0
ns
3
T32’: TCK High Time
25.0
ns
3
@1.7 V
T33’: TCK Low Time
25.0
ns
3
@0.7 V
(0.7 V–1.7 V)
4
(1.7 V–0.7 V)
4
T34’: TCK Rise Time
5.0
ns
3
T35’: TCK Fall Time
5.0
ns
3
T36’: TRST# Pulse Width
40.0
ns
6
Asynchronous
T37’: TDI, TMS Setup Time
5.5
ns
9
5
T38’: TDI, TMS Hold Time
14.5
ns
9
5
T39’: TDO Valid Delay
2.0
13.5
ns
9
6, 7
T40’: TDO Float Delay
28.5
ns
9
6, 7
T41’: All Non-Test Outputs Valid
Delay
2.0
27.5
ns
9
6, 8, 9
T42’: All Non-Test Inputs Setup Time
27.5
ns
9
6, 8, 9
T43’: All Non-Test Inputs Setup Time
5.5
ns
9
5, 8, 9
T44’: All Non-Test Inputs Hold Time
14.5
ns
9
5, 8, 9
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